From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34428) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6Jss-0006bE-TG for qemu-devel@nongnu.org; Mon, 05 Aug 2013 08:27:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6Jsn-0002Bz-6i for qemu-devel@nongnu.org; Mon, 05 Aug 2013 08:27:34 -0400 Received: from hall.aurel32.net ([2001:470:1f0b:4a8::1]:34757) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6Jsm-0002BW-WE for qemu-devel@nongnu.org; Mon, 05 Aug 2013 08:27:29 -0400 Date: Mon, 5 Aug 2013 14:27:19 +0200 From: =?iso-8859-15?Q?Aur=E9lien?= Jarno Message-ID: <20130805122719.GD4193@ohm.aurel32.net> References: <1374941897-11956-1-git-send-email-hpoussin@reactos.org> <51F4218A.1060802@weilnetz.de> <51F430F4.6020708@suse.de> <51F4345D.6080007@weilnetz.de> <51F6D213.8040506@weilnetz.de> <20130804220423.GA4167@ohm.aurel32.net> <51FF35CC.4090700@weilnetz.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <51FF35CC.4090700@weilnetz.de> Subject: Re: [Qemu-devel] [PATCH for-1.6] target-mips: do not raise exceptions when accessing invalid memory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefan Weil Cc: Peter Maydell , =?iso-8859-15?Q?Herv=E9?= Poussineau , Andreas =?iso-8859-15?Q?F=E4rber?= , qemu-devel@nongnu.org On Mon, Aug 05, 2013 at 07:19:08AM +0200, Stefan Weil wrote: > Am 05.08.2013 00:37, schrieb Peter Maydell: > > On 4 August 2013 23:04, Aurélien Jarno wrote: > >> The real hardware probably returns all 1 or all 0 for addresses not > >> decoded to a device. This is what QEMU should model, and it should > >> not trigger a DBE or IBE exception. Looking at the current MIPS > >> documentation, Bus Error is defined as: > >> > >> A bus error exception occurs when an instruction or data access makes a > >> bus request (due to a cache miss or an uncacheable reference) and > >> that request terminates in an error. > >> > >> Older CPU documentation like the R4000 have a more precise definition: > >> > >> A Bus Error exception is raised by board-level circuitry for events such > >> as bus time-out, backplane bus parity errors, and invalid physical memory > >> addresses or access types. > >> > >> As we don't model this kind of errors, we should definitely just not > >> trigger an exception in that case, and even logging the event as > >> unimplemented is probably wrong. > > Well, we certainly can model invalid-physical-address and > > bus-timeout where that's what the board does for accesses > > to non-decoded addresses; but presumably in this case it > > doesn't... > > > > -- PMM > > Is there anybody who has access to physical Malta hardware? > It would be interesting to see whether there is an exception > during the gcmp test or not. > > With latest QEMU, the MIPS Malta system emulation starts > handling the exception caused by the gcmp test, but then > gets a second exception which is fatal (see below). > > There might be something missing in our very simple bios > emulation. Booting YAMON in QEMU also shows the same behaviour, that is trying to access to the 1fbf8008 address and getting a DBE exception, causing it to fail. So it is clearly not due to our simple bios emulation, but rather to the way the I/O are emulated. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net