From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7Mdu-0007yE-3s for qemu-devel@nongnu.org; Thu, 08 Aug 2013 05:36:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V7Mdp-0005Ue-2L for qemu-devel@nongnu.org; Thu, 08 Aug 2013 05:36:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:6157) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7Mdo-0005UW-Lq for qemu-devel@nongnu.org; Thu, 08 Aug 2013 05:36:20 -0400 Date: Thu, 8 Aug 2013 12:37:56 +0300 From: "Michael S. Tsirkin" Message-ID: <20130808093756.GA27298@redhat.com> References: <20130807095019.GA26266@redhat.com> <5202218C.70005@redhat.com> <20130807111031.GC3068@redhat.com> <52023A52.6010208@redhat.com> <20130807123509.GA10670@redhat.com> <520257F8.1080501@redhat.com> <20130807145312.GA14308@redhat.com> <52034F73.4040904@redhat.com> <20130808082212.GA26837@redhat.com> <52035C2F.4040700@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <52035C2F.4040700@redhat.com> Subject: Re: [Qemu-devel] [SeaBIOS] [PATCH] acpi: hide 64-bit PCI hole for Windows XP List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: Paolo Bonzini , seabios@seabios.org, qemu-devel@nongnu.org On Thu, Aug 08, 2013 at 10:51:59AM +0200, Gerd Hoffmann wrote: > On 08/08/13 10:22, Michael S. Tsirkin wrote: > > On Thu, Aug 08, 2013 at 09:57:39AM +0200, Gerd Hoffmann wrote: > >> Hi, > >> > >>>> Huh? The 32bit window is sized according to the installed memory. > >>>> That > >>>> logic is in seabios and you'll try to move it to qemu, using pci-info. > >>>> It wasn't in qemu before ... > >>> > >>> The logic is in hw/i386/pc_piix.c and always was. > >> > >> What exactly you are refering to? > > > > pc_init1 which picks addresses and passes them on to > > i440fx_init. > > Yep. qemu figured where it wants map memory. The unused 32bit address > space goes into the pci hole. cmos memory size is set accordingly. > seabios gets the memory size from cmos, then it knows where the pci hole > starts. seabios rounds it up (i.e. may leave some of it unused) to be > able to cover the complete hole with a single mtrr entry, but that isn't > a issue and can be changed if needed. The mtrr thing is more or less > cosmetical anyway in a virtual machine. > > >> Memory configuration is in the cmos, firmware can figure where it can > >> place pci devices from that. There is no need for a new interface. > > > > The assumption being that whatever is not memory is PCI? > > I'm not sure that's right. > > Maybe not in general, but I'm pretty sure for the x86 chipsets we are > emulating it is. I think this is the basic question. Speaking about PIIX: http://download.intel.com/design/chipsets/datashts/29054901.pdf it only supported 1G RAM and 32 bit PCI. What happened with RAM below 1G is this: top of RAM to 0xfec00000 is PCI - this is emulated correctly fec10000 to ffe00000 is PCI - this is not emulated correctly What happens with RAM >1G is all PV, it doesn't exist on real hardware. Re-adding qemu-devel. Can you please keep it Cc'd? -- MST