From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59759) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7Qws-0002sp-L2 for qemu-devel@nongnu.org; Thu, 08 Aug 2013 10:12:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V7Qwm-0005Z8-CH for qemu-devel@nongnu.org; Thu, 08 Aug 2013 10:12:18 -0400 Received: from mx1.redhat.com ([209.132.183.28]:16925) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7Qwm-0005Z2-3z for qemu-devel@nongnu.org; Thu, 08 Aug 2013 10:12:12 -0400 Date: Thu, 8 Aug 2013 17:13:47 +0300 From: "Michael S. Tsirkin" Message-ID: <20130808141347.GA30200@redhat.com> References: <20130807111031.GC3068@redhat.com> <52023A52.6010208@redhat.com> <20130807123509.GA10670@redhat.com> <520257F8.1080501@redhat.com> <20130807145312.GA14308@redhat.com> <52034F73.4040904@redhat.com> <20130808083732.GB26837@redhat.com> <52035D88.6040002@redhat.com> <20130808095226.GB27298@redhat.com> <5203712C.8090202@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5203712C.8090202@redhat.com> Subject: Re: [Qemu-devel] [SeaBIOS] [PATCH] acpi: hide 64-bit PCI hole for Windows XP List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: Paolo Bonzini , seabios@seabios.org, qemu-devel@nongnu.org On Thu, Aug 08, 2013 at 12:21:32PM +0200, Gerd Hoffmann wrote: > On 08/08/13 11:52, Michael S. Tsirkin wrote: > > On Thu, Aug 08, 2013 at 10:57:44AM +0200, Gerd Hoffmann wrote: > >> On 08/08/13 10:37, Michael S. Tsirkin wrote: > >>> On Thu, Aug 08, 2013 at 09:57:39AM +0200, Gerd Hoffmann wrote: > >>>> Also coreboot and seabios use different values for pmbase. coreboot on > >>>> q35 maps the pmbase below 0x1000. Which surely makes sense. When we > >>>> don't place chipset stuff at 0xb000 we can assign the 0xb000->0xbfff > >>>> window to a pci bridge instead. Re-reading this - if this has value, can't we generalize it and make all firmware behave the same, getting values from QEMU? > >>> > >>> Yes, this might be useful. But I don't think it's required to > >>> use linker to patch ACPI tables for this - we can write ASL code to read > >>> the register back from device configuration, instead. > >> > >> No, we can't, because the address is in the FADT. > >> > >> cheers, > >> Gerd > > > > I see. Yes, PM base is there, this in fact makes it possible > > to patch it by linker in a sane way. > > Exactly. Likewise the mmconf xbar config in the MCFG table. > > But to make addresses usable to devices they also need to be declared in > > the _CRS for the PCI root, correct? Which is code in DSDT. > > Yes, the address ranges used for pci devices (aka 32bit + 64bit pci > window) need to be there. Well, placing in SSDT, then referencing from > DSDT works too, and this is what seabios does today to dynamically > adjust stuff. Fixing up the SSDT using the linker is probably easier as > we generate it anyway. > > cheers, > Gerd Yes but as I said, this makes things messy, since AML encoding for numbers isn't fixed width. -- MST