From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V90v8-00086M-GY for qemu-devel@nongnu.org; Mon, 12 Aug 2013 18:49:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V90v2-00084n-Li for qemu-devel@nongnu.org; Mon, 12 Aug 2013 18:49:02 -0400 Received: from mail-pa0-x22e.google.com ([2607:f8b0:400e:c03::22e]:43205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V90v2-00082w-E6 for qemu-devel@nongnu.org; Mon, 12 Aug 2013 18:48:56 -0400 Received: by mail-pa0-f46.google.com with SMTP id fa1so6166476pad.5 for ; Mon, 12 Aug 2013 15:48:55 -0700 (PDT) Sender: Guenter Roeck Date: Mon, 12 Aug 2013 15:48:53 -0700 From: Guenter Roeck Message-ID: <20130812224853.GA9580@roeck-us.net> References: <20130811220450.GY23006@n2100.arm.linux.org.uk> <52082EF8.10005@roeck-us.net> <20130812164548.GE23006@n2100.arm.linux.org.uk> <20130812200628.GG23006@n2100.arm.linux.org.uk> <20130812212149.GH23006@n2100.arm.linux.org.uk> <20130812221250.GI23006@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130812221250.GI23006@n2100.arm.linux.org.uk> Subject: Re: [Qemu-devel] SCSI bus failures with qemu-arm in kernel 3.8+ List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Russell King - ARM Linux Cc: Peter Maydell , qemu-devel@nongnu.org, "linux-kernel@vger.kernel.org" , Paul Gortmaker , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" On Mon, Aug 12, 2013 at 11:12:50PM +0100, Russell King - ARM Linux wrote: > On Mon, Aug 12, 2013 at 10:36:17PM +0100, Peter Maydell wrote: > > On this point, yes. Equivalent bit from the PB926 TRM: > > http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Cacdijji.html > > > > (There are differences between the PCI controllers on > > the different boards. Differences I know of are: > > * size of the three memory mapped regions > > * whether the top bits of the PCI address come from the top > > or bottom of the IMAP* registers > > I believe (based on some experimentation and an educated guess) > > that these both changed at the same point, but some of the board > > TRMs claim to be part one way part the other, presumably due to > > copy and paste error. In particular PB1176's TRM has a mangled > > description of the IMAP* registers which didn't match what the > > h/w actually did in my testing.) > > Bah, updated TRMs since my version. > > Right, so if I've traced everything correctly, this should work: > > /* > * Slot INTA INTB INTC INTD > * 31 PCI1 PCI2 PCI3 PCI0 > * 30 PCI0 PCI1 PCI2 PCI3 > * 29 PCI3 PCI0 PCI1 PCI2 > */ > return IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3); > Assuming this is what you mean, I added the above code to versatile_map_irq(). It does not work, unfortunately, at least not in qemu 1.4.0. This is what the kernel reports for interrupt numbers: kernel irq result -------------------------------------- 3.10.6: 92 fails 3.10.6+above change: 94 fails 3.10.6+Paul's patch: 91 works Now is this a qemu problem or a kernel problem ? Thanks, Guenter