From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V919x-0003Bm-Nd for qemu-devel@nongnu.org; Mon, 12 Aug 2013 19:04:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V919n-0004zC-CL for qemu-devel@nongnu.org; Mon, 12 Aug 2013 19:04:21 -0400 Received: from mail-pb0-x233.google.com ([2607:f8b0:400e:c01::233]:40967) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V919n-0004yo-5K for qemu-devel@nongnu.org; Mon, 12 Aug 2013 19:04:11 -0400 Received: by mail-pb0-f51.google.com with SMTP id jt11so7263891pbb.24 for ; Mon, 12 Aug 2013 16:04:10 -0700 (PDT) Sender: Guenter Roeck Date: Mon, 12 Aug 2013 16:04:08 -0700 From: Guenter Roeck Message-ID: <20130812230408.GA4420@roeck-us.net> References: <20130811220450.GY23006@n2100.arm.linux.org.uk> <52082EF8.10005@roeck-us.net> <20130812164548.GE23006@n2100.arm.linux.org.uk> <20130812200628.GG23006@n2100.arm.linux.org.uk> <20130812212149.GH23006@n2100.arm.linux.org.uk> <20130812221250.GI23006@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130812221250.GI23006@n2100.arm.linux.org.uk> Subject: Re: [Qemu-devel] SCSI bus failures with qemu-arm in kernel 3.8+ List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Russell King - ARM Linux Cc: Peter Maydell , qemu-devel@nongnu.org, "linux-kernel@vger.kernel.org" , Paul Gortmaker , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" On Mon, Aug 12, 2013 at 11:12:50PM +0100, Russell King - ARM Linux wrote: > On Mon, Aug 12, 2013 at 10:36:17PM +0100, Peter Maydell wrote: > > On this point, yes. Equivalent bit from the PB926 TRM: > > http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Cacdijji.html > > > > (There are differences between the PCI controllers on > > the different boards. Differences I know of are: > > * size of the three memory mapped regions > > * whether the top bits of the PCI address come from the top > > or bottom of the IMAP* registers > > I believe (based on some experimentation and an educated guess) > > that these both changed at the same point, but some of the board > > TRMs claim to be part one way part the other, presumably due to > > copy and paste error. In particular PB1176's TRM has a mangled > > description of the IMAP* registers which didn't match what the > > h/w actually did in my testing.) > > Bah, updated TRMs since my version. > > Right, so if I've traced everything correctly, this should work: > > /* > * Slot INTA INTB INTC INTD > * 31 PCI1 PCI2 PCI3 PCI0 > * 30 PCI0 PCI1 PCI2 PCI3 > * 29 PCI3 PCI0 PCI1 PCI2 > */ > return IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3); > I tried the above with qemu 1.5.2. Success! Hacked diff is below. Can I write that up as clean patch and submit it, or do we need a test on real hardware ? Thanks, Guenter --- diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index e92e5e0..53b4208 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -333,7 +333,11 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) * 26 1 IRQ_SIC_PCI2 * 27 1 IRQ_SIC_PCI3 */ +#if 0 irq = IRQ_SIC_PCI0 + ((slot - 24 + pin - 1) & 3); +#else + irq = IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3); +#endif return irq; }