Re: [Qemu-devel] [PATCH 08/28] mips_malta: do not use isa_mmio

[Aurelien Jarno <aurelien@aurel32.net>]

On Wed, Aug 28, 2013 at 01:03:01PM +0200, Aurelien Jarno wrote:
> On Mon, Jul 22, 2013 at 03:54:18PM +0200, Paolo Bonzini wrote:
> > This fixes endianness bugs in I/O port access.
> 
> It looks like it actually did the reverse, ie introducing endianness
> bugs. With this patch, the pcnet-pci NIC (default NIC card) doesn't work
> any more on big endian Malta, while it still works on little endian
> Malta.
> 
> Reverting this commit fixes the issue for the pcnet card, but it makes
> the IDE controller to fail, likely due to endianness issues.
> 
> This is reproducible using the following kernel and the following line:
> 
> http://ftp.debian.org/debian/dists/wheezy/main/installer-mips/current/images/malta/netboot/vmlinux-3.2.0-4-4kc-malta
> qemu-system-mips -kernel vmlinux-3.2.0-4-4kc-malta -nographic 
> 
> In that case the boot log is:
> 
> | [    0.464000] pcnet32: pcnet32.c:v1.35 21.Apr.2008 tsbogend@alpha.franken.de
> | [    0.464000] PCI: Enabling device 0000:00:0b.0 (0000 -> 0003)
> | [    0.468000] pcnet32: No access methods
> 
> Without this patch, the boot log is:
> 
> | [    0.524000] pcnet32: pcnet32.c:v1.35 21.Apr.2008 tsbogend@alpha.franken.de
> | [    0.524000] PCI: Enabling device 0000:00:0b.0 (0000 -> 0003)
> | [    0.524000] pcnet32: PCnet/PCI II 79C970A at 0x1020, 52:54:00:12:34:56 assigned IRQ 10
> | [    0.528000] pcnet32: eth0: registered as PCnet/PCI II 79C970A
> | [    0.532000] pcnet32: 1 cards_found
> 

It seems to be due to the fact that the pcnet-pci device is declared as
NATIVE_ENDIAN. I don't really understand why. Changing it to
LITTLE_ENDIAN as in the following patch also fixes the problem, but I am
not sure it is correct.

diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
index a893165..865f2f0 100644
--- a/hw/net/pcnet-pci.c
+++ b/hw/net/pcnet-pci.c
@@ -134,7 +134,7 @@ static void pcnet_ioport_write(void *opaque, hwaddr addr,
 static const MemoryRegionOps pcnet_io_ops = {
     .read = pcnet_ioport_read,
     .write = pcnet_ioport_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
@@ -256,7 +256,7 @@ static const MemoryRegionOps pcnet_mmio_ops = {
         .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
         .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
     },
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net