From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56770) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGWU1-0007W6-MA for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:56:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGWTv-00023V-Bm for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:56:05 -0400 Received: from mx1.redhat.com ([209.132.183.28]:26802) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGWTv-000230-4Z for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:55:59 -0400 Date: Mon, 2 Sep 2013 18:57:57 +0300 From: "Michael S. Tsirkin" Message-ID: <20130902155757.GB4691@redhat.com> References: <1378131189-25538-1-git-send-email-marcel.a@redhat.com> <1378131189-25538-4-git-send-email-marcel.a@redhat.com> <1378136553.2640.34.camel@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1378136553.2640.34.camel@localhost.localdomain> Subject: Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum Cc: Peter Maydell , Anthony Liguori , QEMU Developers , Andreas =?iso-8859-1?Q?F=E4rber?= , Paolo Bonzini On Mon, Sep 02, 2013 at 06:42:33PM +0300, Marcel Apfelbaum wrote: > On Mon, 2013-09-02 at 15:39 +0100, Peter Maydell wrote: > > On 2 September 2013 15:13, Marcel Apfelbaum wrote: > > > Added a memory region that has negative priority and > > > extends over all the pci adddress space. This region will > > > "catch" all the accesses to the unassigned pci > > > addresses and it will be possible to emulate the > > > master abort scenario (When no device on the bus claims > > > the transaction). > > > > > > Signed-off-by: Marcel Apfelbaum > > > --- > > > hw/pci-host/piix.c | 8 ++++++++ > > > hw/pci-host/q35.c | 19 ++++++++++++++++--- > > > include/hw/pci-host/q35.h | 1 + > > > > This is happening at the wrong layer -- you want this memory > > region to be created and managed in the PCI core code so that > > we get correct PCI-spec behaviour for all our PCI controllers, > > not just the two x86 ones you've changed here.pci_address_space > I saw that the memory regions are part of the Host state and > duplicated for each host type(like pci_address_space). > Question, why are not pci_address_space and pci_hole present > in a core layer? I think we can move them out to core. > > I followed the existing code; from what you are saying > I understand that also the existing memory regions > like the one mentioned above should be moved in > the core layer, right? > Marcel pci hole is a PC thing. > > > > -- PMM > > >