From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57314) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGWWC-0000wV-VU for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:58:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGWW6-0002lE-Vx for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:58:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:19497) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGWW6-0002lA-Mr for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:58:14 -0400 Date: Mon, 2 Sep 2013 19:00:13 +0300 From: "Michael S. Tsirkin" Message-ID: <20130902160013.GC4691@redhat.com> References: <1378131189-25538-1-git-send-email-marcel.a@redhat.com> <1378131189-25538-4-git-send-email-marcel.a@redhat.com> <1378136553.2640.34.camel@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paolo Bonzini , Anthony Liguori , QEMU Developers , Andreas =?iso-8859-1?Q?F=E4rber?= , Marcel Apfelbaum On Mon, Sep 02, 2013 at 04:53:50PM +0100, Peter Maydell wrote: > On 2 September 2013 16:42, Marcel Apfelbaum wrote: > > On Mon, 2013-09-02 at 15:39 +0100, Peter Maydell wrote: > >> This is happening at the wrong layer -- you want this memory > >> region to be created and managed in the PCI core code so that > >> we get correct PCI-spec behaviour for all our PCI controllers, > >> not just the two x86 ones you've changed here.pci_address_space > > I saw that the memory regions are part of the Host state and > > duplicated for each host type(like pci_address_space). > > Question, why are not pci_address_space and pci_hole present > > in a core layer? > > > > I followed the existing code; from what you are saying > > I understand that also the existing memory regions > > like the one mentioned above should be moved in > > the core layer, right? > > Ideally, yes, I think so. However that's not particularly > a requirement for the changes you're trying to make here: > at the moment what happens is that the pci controller > creates the PCI memory and io memory regions (or cheats > by reusing the system memory space[*]), passes them to > the PCI core code (via pci_bus_new) and then they're > the PCI code's responsibility to manage. So in the PCI > code you can ignore where they came from when you're > deciding how to manage these containers (and in this case > what you do is just create your default region and map > it in to the container at a suitable priority). > > [*] I'm pretty sure this is a bug in all platforms that do it. > > -- PMM Well as usual this cheat originated with PIIX. AFAIK PIIX actually has a shared bus for memory and PCI so this is not a bug there, I think. -- MST