From: Antony Pavlov <antonynpavlov@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [RFC v4 4/5] hw/arm/digic: add UART support
Date: Sat, 7 Sep 2013 09:45:13 +0400 [thread overview]
Message-ID: <20130907094513.f175c6b95d50c0855f7e6348@gmail.com> (raw)
In-Reply-To: <CAFEAcA_Fuf4dEcK8jTYYXdCoe21bi6J9PdaoJTuaNY1u8PgdaQ@mail.gmail.com>
On Fri, 6 Sep 2013 14:40:14 +0100
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 6 September 2013 14:00, Antony Pavlov <antonynpavlov@gmail.com> wrote:
> > On Fri, 6 Sep 2013 08:25:20 +0100
> > Peter Maydell <peter.maydell@linaro.org> wrote:
> >> You can deduce its existence though -- does the
> >> UART let you feed two or three characters to it
> >> at faster than whatever the serial line speed is
> >> before it sets the "stop sending me bits" status
> >> bit, or does it stop after the first?
> >
> > No, I can't :)
> >
> > How can I check this mysterious "stop sending me bits" status bit?
> > Do you mean the UART hardware flow control pin?
>
> I meant ST_TX_RDY, but looking again at the
> docs perhaps I misinterpreted it. Do you really
> have to do:
> * write byte to TX register
> * set TX_RDY bit in status register
>
> to get it to send out a byte?
I don't want publish Canon firmware disassembled listings and discuss it
in the maillist for legal reasons.
But Canon A1100 firmware can use this routine:
1. wait TX_RDY bit in status register;
2. write TX_RDY and some other (unknown behaviour) bit to status register;
3. write byte to TX register.
IMHO the step 2 is bizarre.
You can easely check me: the disassembly instructions and firmware images can
be found via CHDK site. A puts()-like routine can be found at 0xffff18f0
in the Canon A1100IS firmware image.
> I was expecting a more standard UART interface
> which is typically:
> * write byte to TX register
> * if the UART is unable to accept any more
> bytes (ie FIFO full, or just immediately if
> no FIFO present) it clears TX_RDY
> * software has to wait for TX_RDY to be set
> before writing another byte to TX
IMHO the more standart UART outc() routune is:
* wait for UART "transmitter is ready to send next char" flag;
* write char to TX register.
E.g. see
https://github.com/frantony/barebox/blob/master/arch/mips/include/asm/debug_ll_ns16550.h#L60
or
https://github.com/frantony/barebox/blob/master/arch/arm/mach-imx/include/mach/debug_ll.h#L49
--
Best regards,
Antony Pavlov
next prev parent reply other threads:[~2013-09-07 5:47 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-05 7:52 [Qemu-devel] [RFC v4 0/5] hw/arm: add initial support for Canon DIGIC SoC Antony Pavlov
2013-09-05 7:52 ` [Qemu-devel] [RFC v4 1/5] hw/arm: add very " Antony Pavlov
2013-09-05 18:08 ` Andreas Färber
2013-09-05 21:23 ` Antony Pavlov
2013-09-05 21:38 ` Andreas Färber
2013-09-06 5:01 ` Antony Pavlov
2013-09-05 7:52 ` [Qemu-devel] [RFC v4 2/5] hw/arm/digic: prepare DIGIC-based boards support Antony Pavlov
2013-09-05 17:54 ` Peter Maydell
2013-09-06 7:12 ` Antony Pavlov
2013-09-05 7:52 ` [Qemu-devel] [RFC v4 3/5] hw/arm/digic: add timer support Antony Pavlov
2013-09-05 7:52 ` [Qemu-devel] [RFC v4 4/5] hw/arm/digic: add UART support Antony Pavlov
2013-09-05 18:17 ` Peter Maydell
2013-09-06 6:54 ` Antony Pavlov
2013-09-06 7:25 ` Peter Maydell
2013-09-06 13:00 ` Antony Pavlov
2013-09-06 13:40 ` Peter Maydell
2013-09-07 5:45 ` Antony Pavlov [this message]
2013-09-07 8:33 ` Peter Maydell
2013-09-05 7:52 ` [Qemu-devel] [RFC v4 5/5] hw/arm/digic: add NOR ROM support Antony Pavlov
2013-09-05 18:19 ` Peter Maydell
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