From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58036) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJRNp-0005LF-4A for qemu-devel@nongnu.org; Tue, 10 Sep 2013 13:05:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VJRNi-0007ZH-NF for qemu-devel@nongnu.org; Tue, 10 Sep 2013 13:05:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:19673) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJRNi-0007Z2-Fo for qemu-devel@nongnu.org; Tue, 10 Sep 2013 13:05:38 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r8AH5bvH023630 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 10 Sep 2013 13:05:37 -0400 Date: Tue, 10 Sep 2013 19:05:10 +0200 From: Igor Mammedov Message-ID: <20130910190510.36f3fbc9@nial.usersys.redhat.com> In-Reply-To: <20130910135041.GC2196@redhat.com> References: <1378291667-8516-1-git-send-email-mst@redhat.com> <1378291667-8516-5-git-send-email-mst@redhat.com> <20130910154003.4d49c2a6@nial.usersys.redhat.com> <20130910135041.GC2196@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 4/6] pci: add helper to retrieve the 64-bit range List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: qemu-devel@nongnu.org On Tue, 10 Sep 2013 16:50:41 +0300 "Michael S. Tsirkin" wrote: > On Tue, Sep 10, 2013 at 03:40:03PM +0200, Igor Mammedov wrote: > > On Wed, 4 Sep 2013 13:48:37 +0300 > > "Michael S. Tsirkin" wrote: > > > > > Signed-off-by: Michael S. Tsirkin > > > --- > > > include/hw/pci/pci.h | 1 + > > > hw/pci/pci.c | 43 +++++++++++++++++++++++++++++++++++++++++++ > > > 2 files changed, 44 insertions(+) > > > > > > diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > > > index 2374aa9..7be93ae 100644 > > > --- a/include/hw/pci/pci.h > > > +++ b/include/hw/pci/pci.h > > > @@ -397,6 +397,7 @@ const char *pci_root_bus_path(PCIDevice *dev); > > > PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); > > > int pci_qdev_find_device(const char *id, PCIDevice **pdev); > > > PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr); > > > +void pci_bus_get_w64_range(PCIBus *bus, Range *range); > > > > > > int pci_parse_devaddr(const char *addr, int *domp, int *busp, > > > unsigned int *slotp, unsigned int *funcp); > > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > > > index 8c33352..d9f9bdf 100644 > > > --- a/hw/pci/pci.c > > > +++ b/hw/pci/pci.c > > > @@ -2257,6 +2257,49 @@ void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) > > > bus->iommu_opaque = opaque; > > > } > > > > > > +static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) > > > +{ > > > + Range *range = opaque; > > > + PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); > > > + uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); > > > + int r; > > > + > > > + if (!(cmd & PCI_COMMAND_MEMORY)) { > > > + return; > > > + } > > > + > > > + if (pc->is_bridge) { > > > + pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); > > what guaranties that 'base' won't be below 4Gb > > Hmm, this needs some thought. > > > and be above '4Gb + above_4g_mem_size'? > > This one is harmless - guest will only hurt itself if > it misconfigures the bridge like this. start of w64 is hardcoded in QEMU and Seabios as (4Gb+above_4gb_ram_size), so maybe there is no need to update/modify it at all? > > > > + pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); > > > + > > > + if (limit >= base) { > > > + Range pref_range; > > > + pref_range.begin = base; > > > + pref_range.end = limit + 1; > > > + range_extend(range, &pref_range); > > > + } > > > + } > > > + for (r = 0; r < PCI_NUM_REGIONS; ++r) { > > > + PCIIORegion *region = &dev->io_regions[r]; > > > + Range region_range; > > > + > > > + if (!region->size || > > > + (region->type & PCI_BASE_ADDRESS_SPACE_IO) || > > > + !(region->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { > > > + continue; > > > + } > > > + region_range.begin = pci_get_quad(dev->config + pci_bar(dev, r)); > > > + region_range.end = region_range.begin + region->size; > > > + range_extend(range, ®ion_range); > > > + } > > > +} > > > + > > > +void pci_bus_get_w64_range(PCIBus *bus, Range *range) > > > +{ > > > + range->begin = range->end = 0; > > > + pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); > > > +} > > > + > > > static const TypeInfo pci_device_type_info = { > > > .name = TYPE_PCI_DEVICE, > > > .parent = TYPE_DEVICE,