From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VQ1jW-0003Ab-Mu for qemu-devel@nongnu.org; Sat, 28 Sep 2013 17:07:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VQ1jR-0005YF-NU for qemu-devel@nongnu.org; Sat, 28 Sep 2013 17:07:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37166) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VQ1jR-0005Y4-FO for qemu-devel@nongnu.org; Sat, 28 Sep 2013 17:07:17 -0400 Date: Sun, 29 Sep 2013 00:09:35 +0300 From: "Michael S. Tsirkin" Message-ID: <20130928210935.GA26613@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH] ahci: set ahci mode on reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Kevin Wolf , Paolo Bonzini , Andreas =?iso-8859-1?Q?F=E4rber?= , Anthony Liguori ATM we set AHCI mode on 1st GHC write. Spec says we should set it on reset. Signed-off-by: Michael S. Tsirkin --- hw/ide/ahci.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index a71a4ca..a8be62c 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1198,7 +1198,15 @@ void ahci_reset(AHCIState *s) int i; s->control_regs.irqstatus = 0; - s->control_regs.ghc = 0; + /* AHCI Enable (AE) + * The implementation of this bit is dependent upon the value of the + * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and + * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be + * read-only and shall have a reset value of '1'. + * + * We set HOST_CAP_AHCI so we must enable AHCI at reset. + */ + s->control_regs.ghc = HOST_CTL_AHCI_EN; for (i = 0; i < s->ports; i++) { pr = &s->dev[i].port_regs; -- MST