From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52098) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VYZpk-0006t3-CE for qemu-devel@nongnu.org; Tue, 22 Oct 2013 07:09:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VYZpc-0005db-TF for qemu-devel@nongnu.org; Tue, 22 Oct 2013 07:09:08 -0400 Received: from ozlabs.org ([2402:b800:7003:1:1::1]:35879) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VYZpc-0005dN-HT for qemu-devel@nongnu.org; Tue, 22 Oct 2013 07:09:00 -0400 Date: Tue, 22 Oct 2013 22:09:00 +1100 From: Anton Blanchard Message-ID: <20131022220900.1283b8ff@kryten> In-Reply-To: <20131022220546.2a20d02a@kryten> References: <20131022220546.2a20d02a@kryten> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 6/7] Add stxvd2x List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: agraf@suse.de Cc: tommusta@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, rth@twiddle.net From: Tom Musta This patch adds the stxvd2x instruction. Signed-off-by: Tom Musta Signed-off-by: Anton Blanchard --- Index: b/target-ppc/translate.c =================================================================== --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7023,6 +7023,22 @@ static void gen_lxvd2x(DisasContext *ctx tcg_temp_free(EA); } +static void gen_stxvd2x(DisasContext *ctx) +{ + TCGv EA; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); + tcg_gen_addi_tl(EA, EA, 8); + gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); + tcg_temp_free(EA); +} + /*** SPE extension ***/ /* Register moves */ @@ -9474,6 +9490,8 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), + #undef GEN_SPE #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)