* [Qemu-devel] [PATCH 2/7] Add MSR VSX and Associated Exception
2013-10-22 11:05 [Qemu-devel] [PATCH 1/7] Declare and Enable VSX Anton Blanchard
@ 2013-10-22 11:06 ` Anton Blanchard
2013-10-22 15:10 ` Richard Henderson
2013-10-22 11:06 ` [Qemu-devel] [PATCH 3/7] Add VSX Instruction Decoders Anton Blanchard
` (5 subsequent siblings)
6 siblings, 1 reply; 9+ messages in thread
From: Anton Blanchard @ 2013-10-22 11:06 UTC (permalink / raw)
To: agraf; +Cc: tommusta, qemu-ppc, qemu-devel, rth
From: Tom Musta <tommusta@gmail.com>
This patch adds support for the VSX bit of the PowerPC Machine
State Register (MSR) as well as the corresponding VSX Unavailable
exception.
The VSX bit is added to the defined bits masks of the Power7 and
Power8 CPU models.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: b/target-ppc/cpu.h
===================================================================
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -236,6 +236,8 @@ enum {
POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
+ /* VSX Unavailable (Power ISA 2.06 and later) */
+ POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
/* EOL */
POWERPC_EXCP_NB = 96,
/* QEMU exceptions: used internally during code translation */
@@ -427,6 +429,7 @@ struct ppc_slb_t {
#define MSR_VR 25 /* altivec available x hflags */
#define MSR_SPE 25 /* SPE enable for BookE x hflags */
#define MSR_AP 23 /* Access privilege state on 602 hflags */
+#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
#define MSR_KEY 19 /* key bit on 603e */
#define MSR_POW 18 /* Power management */
@@ -467,6 +470,7 @@ struct ppc_slb_t {
#define msr_vr ((env->msr >> MSR_VR) & 1)
#define msr_spe ((env->msr >> MSR_SPE) & 1)
#define msr_ap ((env->msr >> MSR_AP) & 1)
+#define msr_vsx ((env->msr >> MSR_VSX) & 1)
#define msr_sa ((env->msr >> MSR_SA) & 1)
#define msr_key ((env->msr >> MSR_KEY) & 1)
#define msr_pow ((env->msr >> MSR_POW) & 1)
Index: b/target-ppc/excp_helper.c
===================================================================
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -390,6 +390,11 @@ static inline void powerpc_excp(PowerPCC
new_msr |= (target_ulong)MSR_HVB;
}
goto store_current;
+ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
+ if (lpes1 == 0) {
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+ goto store_current;
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
LOG_EXCP("PIT exception\n");
goto store_next;
Index: b/target-ppc/translate.c
===================================================================
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -199,6 +199,7 @@ typedef struct DisasContext {
#endif
int fpu_enabled;
int altivec_enabled;
+ int vsx_enabled;
int spe_enabled;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
@@ -9763,6 +9764,11 @@ static inline void gen_intermediate_code
ctx.altivec_enabled = msr_vr;
else
ctx.altivec_enabled = 0;
+ if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
+ ctx.vsx_enabled = msr_vsx;
+ } else {
+ ctx.vsx_enabled = 0;
+ }
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
ctx.singlestep_enabled = CPU_SINGLE_STEP;
else
Index: b/target-ppc/translate_init.c
===================================================================
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3061,6 +3061,7 @@ static void init_excp_POWER7 (CPUPPCStat
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
+ env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
@@ -7232,7 +7233,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc,
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
- pcc->msr_mask = 0x800000000204FF37ULL;
+ pcc->msr_mask = 0x800000000284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -7267,7 +7268,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc,
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
- pcc->msr_mask = 0x800000000204FF36ULL;
+ pcc->msr_mask = 0x800000000284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH 2/7] Add MSR VSX and Associated Exception
2013-10-22 11:06 ` [Qemu-devel] [PATCH 2/7] Add MSR VSX and Associated Exception Anton Blanchard
@ 2013-10-22 15:10 ` Richard Henderson
0 siblings, 0 replies; 9+ messages in thread
From: Richard Henderson @ 2013-10-22 15:10 UTC (permalink / raw)
To: Anton Blanchard, agraf; +Cc: tommusta, qemu-ppc, qemu-devel
On 10/22/2013 04:06 AM, Anton Blanchard wrote:
> From: Tom Musta <tommusta@gmail.com>
>
> This patch adds support for the VSX bit of the PowerPC Machine
> State Register (MSR) as well as the corresponding VSX Unavailable
> exception.
>
> The VSX bit is added to the defined bits masks of the Power7 and
> Power8 CPU models.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
>
> Index: b/target-ppc/cpu.h
> ===================================================================
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -236,6 +236,8 @@ enum {
> POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
> POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
> POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
> + /* VSX Unavailable (Power ISA 2.06 and later) */
> + POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
> /* EOL */
> POWERPC_EXCP_NB = 96,
> /* QEMU exceptions: used internally during code translation */
> @@ -427,6 +429,7 @@ struct ppc_slb_t {
> #define MSR_VR 25 /* altivec available x hflags */
> #define MSR_SPE 25 /* SPE enable for BookE x hflags */
> #define MSR_AP 23 /* Access privilege state on 602 hflags */
> +#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
> #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
> #define MSR_KEY 19 /* key bit on 603e */
> #define MSR_POW 18 /* Power management */
> @@ -467,6 +470,7 @@ struct ppc_slb_t {
> #define msr_vr ((env->msr >> MSR_VR) & 1)
> #define msr_spe ((env->msr >> MSR_SPE) & 1)
> #define msr_ap ((env->msr >> MSR_AP) & 1)
> +#define msr_vsx ((env->msr >> MSR_VSX) & 1)
> #define msr_sa ((env->msr >> MSR_SA) & 1)
> #define msr_key ((env->msr >> MSR_KEY) & 1)
> #define msr_pow ((env->msr >> MSR_POW) & 1)
> Index: b/target-ppc/excp_helper.c
> ===================================================================
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -390,6 +390,11 @@ static inline void powerpc_excp(PowerPCC
> new_msr |= (target_ulong)MSR_HVB;
> }
> goto store_current;
> + case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
> + if (lpes1 == 0) {
> + new_msr |= (target_ulong)MSR_HVB;
> + }
> + goto store_current;
> case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> LOG_EXCP("PIT exception\n");
> goto store_next;
> Index: b/target-ppc/translate.c
> ===================================================================
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -199,6 +199,7 @@ typedef struct DisasContext {
> #endif
> int fpu_enabled;
> int altivec_enabled;
> + int vsx_enabled;
> int spe_enabled;
> ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
> int singlestep_enabled;
> @@ -9763,6 +9764,11 @@ static inline void gen_intermediate_code
> ctx.altivec_enabled = msr_vr;
> else
> ctx.altivec_enabled = 0;
> + if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
> + ctx.vsx_enabled = msr_vsx;
> + } else {
> + ctx.vsx_enabled = 0;
> + }
In order to get correct code generation when the msr changes,
one has to adjust the TB flags. Which for target-ppc means
adjusting env->hflags.
See hreg_compute_hflags.
Ideally, target-ppc would initialize these ctx bits from tb->flags
instead of env->msr to make this obvious. But so long as the two
are in sync it's not technically a bug.
r~
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 3/7] Add VSX Instruction Decoders
2013-10-22 11:05 [Qemu-devel] [PATCH 1/7] Declare and Enable VSX Anton Blanchard
2013-10-22 11:06 ` [Qemu-devel] [PATCH 2/7] Add MSR VSX and Associated Exception Anton Blanchard
@ 2013-10-22 11:06 ` Anton Blanchard
2013-10-22 11:07 ` [Qemu-devel] [PATCH 4/7] Add VSR to Global Registers Anton Blanchard
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Anton Blanchard @ 2013-10-22 11:06 UTC (permalink / raw)
To: agraf; +Cc: tommusta, qemu-ppc, qemu-devel, rth
From: Tom Musta <tommusta@gmail.com>
This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM. The first four are split fields and a general helper for
these types of fields is also added.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: b/target-ppc/translate.c
===================================================================
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -370,6 +370,12 @@ static inline int32_t name(uint32_t opco
return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
}
+#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
+static inline uint32_t name(uint32_t opcode) \
+{ \
+ return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
+ ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
+}
/* Opcode part 1 */
EXTRACT_HELPER(opc1, 26, 6);
/* Opcode part 2 */
@@ -484,6 +490,11 @@ static inline target_ulong MASK(uint32_t
return ret;
}
+EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
+EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
+EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
+EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
+EXTRACT_HELPER(DM, 8, 2);
/*****************************************************************************/
/* PowerPC instructions table */
^ permalink raw reply [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 4/7] Add VSR to Global Registers
2013-10-22 11:05 [Qemu-devel] [PATCH 1/7] Declare and Enable VSX Anton Blanchard
2013-10-22 11:06 ` [Qemu-devel] [PATCH 2/7] Add MSR VSX and Associated Exception Anton Blanchard
2013-10-22 11:06 ` [Qemu-devel] [PATCH 3/7] Add VSX Instruction Decoders Anton Blanchard
@ 2013-10-22 11:07 ` Anton Blanchard
2013-10-22 11:08 ` [Qemu-devel] [PATCH 5/7] Add lxvd2x Anton Blanchard
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Anton Blanchard @ 2013-10-22 11:07 UTC (permalink / raw)
To: agraf; +Cc: tommusta, qemu-ppc, qemu-devel, rth
From: Tom Musta <tommusta@gmail.com>
This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of the first 32 VSRs to
the list of global register indices. The upper halves of the first
32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs
are already defined via the cpu_avrh[] and cpu_avrl[] arrays.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: b/target-ppc/translate.c
===================================================================
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -51,6 +51,7 @@ static char cpu_reg_names[10*3 + 22*4 /*
#endif
+ 10*4 + 22*5 /* FPR */
+ 2*(10*6 + 22*7) /* AVRh, AVRl */
+ + 10*5 + 22*6 /* VSR */
+ 8*5 /* CRF */];
static TCGv cpu_gpr[32];
#if !defined(TARGET_PPC64)
@@ -58,6 +59,7 @@ static TCGv cpu_gprh[32];
#endif
static TCGv_i64 cpu_fpr[32];
static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
+static TCGv_i64 cpu_vsr[32];
static TCGv_i32 cpu_crf[8];
static TCGv cpu_nip;
static TCGv cpu_msr;
@@ -137,6 +139,11 @@ void ppc_translate_init(void)
#endif
p += (i < 10) ? 6 : 7;
cpu_reg_names_size -= (i < 10) ? 6 : 7;
+ snprintf(p, cpu_reg_names_size, "vsr%d", i);
+ cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUPPCState, vsr[i]), p);
+ p += (i < 10) ? 5 : 6;
+ cpu_reg_names_size -= (i < 10) ? 5 : 6;
}
cpu_nip = tcg_global_mem_new(TCG_AREG0,
@@ -6980,6 +6987,26 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20
GEN_VAFORM_PAIRED(vsel, vperm, 21)
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
+/*** VSX extension ***/
+
+static inline TCGv_i64 cpu_vsrh(int n)
+{
+ if (n < 32) {
+ return cpu_fpr[n];
+ } else {
+ return cpu_avrh[n-32];
+ }
+}
+
+static inline TCGv_i64 cpu_vsrl(int n)
+{
+ if (n < 32) {
+ return cpu_vsr[n];
+ } else {
+ return cpu_avrl[n-32];
+ }
+}
+
/*** SPE extension ***/
/* Register moves */
^ permalink raw reply [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 5/7] Add lxvd2x
2013-10-22 11:05 [Qemu-devel] [PATCH 1/7] Declare and Enable VSX Anton Blanchard
` (2 preceding siblings ...)
2013-10-22 11:07 ` [Qemu-devel] [PATCH 4/7] Add VSR to Global Registers Anton Blanchard
@ 2013-10-22 11:08 ` Anton Blanchard
2013-10-22 11:09 ` [Qemu-devel] [PATCH 6/7] Add stxvd2x Anton Blanchard
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Anton Blanchard @ 2013-10-22 11:08 UTC (permalink / raw)
To: agraf; +Cc: tommusta, qemu-ppc, qemu-devel, rth
From: Tom Musta <tommusta@gmail.com>
This patch adds the lxvd2x instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: b/target-ppc/translate.c
===================================================================
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7007,6 +7007,22 @@ static inline TCGv_i64 cpu_vsrl(int n)
}
}
+static void gen_lxvd2x(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
+ tcg_temp_free(EA);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9456,6 +9472,8 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20
GEN_VAFORM_PAIRED(vsel, vperm, 21),
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
+GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+
#undef GEN_SPE
#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
^ permalink raw reply [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 6/7] Add stxvd2x
2013-10-22 11:05 [Qemu-devel] [PATCH 1/7] Declare and Enable VSX Anton Blanchard
` (3 preceding siblings ...)
2013-10-22 11:08 ` [Qemu-devel] [PATCH 5/7] Add lxvd2x Anton Blanchard
@ 2013-10-22 11:09 ` Anton Blanchard
2013-10-22 11:09 ` [Qemu-devel] [PATCH 7/7] Add xxpermdi Anton Blanchard
2013-12-03 16:10 ` [Qemu-devel] [PATCH 1/7] Declare and Enable VSX Tom Musta
6 siblings, 0 replies; 9+ messages in thread
From: Anton Blanchard @ 2013-10-22 11:09 UTC (permalink / raw)
To: agraf; +Cc: tommusta, qemu-ppc, qemu-devel, rth
From: Tom Musta <tommusta@gmail.com>
This patch adds the stxvd2x instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: b/target-ppc/translate.c
===================================================================
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7023,6 +7023,22 @@ static void gen_lxvd2x(DisasContext *ctx
tcg_temp_free(EA);
}
+static void gen_stxvd2x(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
+ tcg_temp_free(EA);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9474,6 +9490,8 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
+
#undef GEN_SPE
#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
^ permalink raw reply [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 7/7] Add xxpermdi
2013-10-22 11:05 [Qemu-devel] [PATCH 1/7] Declare and Enable VSX Anton Blanchard
` (4 preceding siblings ...)
2013-10-22 11:09 ` [Qemu-devel] [PATCH 6/7] Add stxvd2x Anton Blanchard
@ 2013-10-22 11:09 ` Anton Blanchard
2013-12-03 16:10 ` [Qemu-devel] [PATCH 1/7] Declare and Enable VSX Tom Musta
6 siblings, 0 replies; 9+ messages in thread
From: Anton Blanchard @ 2013-10-22 11:09 UTC (permalink / raw)
To: agraf; +Cc: tommusta, qemu-ppc, qemu-devel, rth
From: Tom Musta <tommusta@gmail.com>
This patch adds the xxpermdi instruction. The instruction
uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
and BX). This results in overloading of the opcode table
with aliases, which can be seen in the GEN_XX3FORM_DM
macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: b/target-ppc/translate.c
===================================================================
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7039,10 +7039,28 @@ static void gen_stxvd2x(DisasContext *ct
tcg_temp_free(EA);
}
+static void gen_xxpermdi(DisasContext *ctx)
+{
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+
+ if ((DM(ctx->opcode) & 2) == 0) {
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
+ } else {
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
+ }
+ if ((DM(ctx->opcode) & 1) == 0) {
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
+ } else {
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
+ }
+}
+
/*** SPE extension ***/
/* Register moves */
-
static inline void gen_evmra(DisasContext *ctx)
{
@@ -9492,6 +9510,27 @@ GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A,
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
+#undef GEN_XX3FORM_DM
+#define GEN_XX3FORM_DM(name, opc2, opc3) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
+
+GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
+
#undef GEN_SPE
#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH 1/7] Declare and Enable VSX
2013-10-22 11:05 [Qemu-devel] [PATCH 1/7] Declare and Enable VSX Anton Blanchard
` (5 preceding siblings ...)
2013-10-22 11:09 ` [Qemu-devel] [PATCH 7/7] Add xxpermdi Anton Blanchard
@ 2013-12-03 16:10 ` Tom Musta
6 siblings, 0 replies; 9+ messages in thread
From: Tom Musta @ 2013-12-03 16:10 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, Anton Blanchard, Alexander Graf
On 10/22/2013 6:05 AM, Anton Blanchard wrote:
> From: Tom Musta <tommusta@gmail.com>
>
> This patch adds the flag POWERPC_FLAG_VSX to the list of defined
> flags and also adds this flag to the list of supported features of
> the Power7 and Power8 CPUs. Additionally, the VSX instructions
> are added to the list of TCG-enabled instruction.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
<snip>
>
Ping.
^ permalink raw reply [flat|nested] 9+ messages in thread