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* [Qemu-devel] Does QEMU support MIPS SMP2 malta board?
@ 2013-10-31  3:47 Nancy
  2013-11-07 16:13 ` Edgar E. Iglesias
  0 siblings, 1 reply; 5+ messages in thread
From: Nancy @ 2013-10-31  3:47 UTC (permalink / raw)
  To: qemu-discuss, qemu-devel

Hi,

Does QEMU support MIPS smp 2 malta board?

$ qemu-system-mipsel -M malta -kernel vmlinux -initrd  ramfs.cpio.gz \
-append "console=ttyS0 root=/dev/ram0 maxcpus=2"  -nographic -s \
-smp 2

Linux version 3.11.0-rc6 (yrtan@localhost.localdomain) (gcc version
4.7.2 (Sourcery CodeBench Lite 2012.09-99) ) #4 SMP Thu Oct 31
09:21:01 CST 2013
bootconsole [early0] enabled
CPU revision is: 00019300 (MIPS 24Kc)
FPU revision is: 00739300
Software DMA cache coherency enabled
Determined physical RAM map:
 memory: 00001000 @ 00000000 (reserved)
 memory: 000ef000 @ 00001000 (ROM data)
 memory: 004cf000 @ 000f0000 (reserved)
 memory: 07a41000 @ 005bf000 (usable)
Wasting 47072 bytes for tracking 1471 unused pages
Initial ramdisk at: 0x805bf000 (2614602 bytes)
Zone ranges:
  DMA      [mem 0x00000000-0x00ffffff]
  Normal   [mem 0x01000000-0x07ffffff]
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x00000000-0x07ffffff]
Primary instruction cache 2kB, VIPT, 2-way, linesize 16 bytes.
Primary data cache 2kB, 2-way, VIPT, no aliases, linesize 16 bytes
PERCPU: Embedded 7 pages/cpu @81103000 s6656 r8192 d13824 u32768
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
Kernel command line: rd_start=0xffffffff805bf000 rd_size=2614602
console=ttyS0 root=/dev/ram0
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Writing ErrCtl register=00000000
Readback ErrCtl register=00000000
Memory: 121464K/131072K available (3668K kernel code, 201K rwdata,
648K rodata, 208K init, 122K bss, 9608K reserved)
Hierarchical RCU implementation.
    RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
NR_IRQS:256
Linux version 3.11.0-rc6 (yrtan@localhost.localdomain) (gcc version
4.7.2 (Sourcery CodeBench Lite 2012.09-99) ) #4 SMP Thu Oct 31
09:21:01 CST 2013
bootconsole [early0] enabled
CPU revision is: 00019300 (MIPS 24Kc)
FPU revision is: 00739300
Skipping PCI bus scan due to resource conflict
Software DMA cache coherency enabled
Determined physical RAM map:
 memory: 00001000 @ 00000000 (reserved)
 memory: 000ef000 @ 00001000 (ROM data)
 memory: 004cf000 @ 000f0000 (reserved)
 memory: 07a41000 @ 005bf000 (usable)
Wasting 47072 bytes for tracking 1471 unused pages
Initrd not found or empty - disabling initrd
Zone ranges:
  DMA      [mem 0x00000000-0x00ffffff]
  Normal   [mem 0x01000000-0x07ffffff]
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x00000000-0x07ffffff]
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at mm/page_alloc.c:4796 free_area_init_node+0x38c/0x3c0()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.11.0-rc6 #4
Stack : 00000006 00000004 00000000 00000000 00000000 00000000 805ae5b6 00000037
      805b0000 00000000 8057783c 80551280 00000000 00000000 00000000 00000000
      00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
      00000000 00000000 00000000 8053bd00 8053bd14 804eee0c 80550fa7 8016c714
      805b0000 804eee0c 00000000 00000000 80551280 805a3f1c 80550f66 8053bc90
      ...
Call Trace:
[<801093a8>] show_stack+0x64/0x7c
[<8048f840>] dump_stack+0x64/0x84
[<8012d374>] warn_slowpath_common+0x84/0xb4
[<8012d3bc>] warn_slowpath_null+0x18/0x24
[<8057783c>] free_area_init_node+0x38c/0x3c0
[<80577d9c>] free_area_init_nodes+0x518/0x554
[<805732a4>] paging_init+0x2c/0x38
[<805715f8>] setup_arch+0x488/0x60c
[<8056c63c>] start_kernel+0x84/0x3d4
[<8048bf70>] kernel_entry+0x0/0xa8

---[ end trace 4eaa2a86a8e2da22 ]---
Primary instruction cache 2kB, VIPT, 2-way, linesize 16 bytes.
Primary data cache 2kB, 2-way, VIPT, no aliases, linesize 16 bytes

There's no problem while I removing "-smp 2" option. (plus the kernel
MIPS configure file " malta_defconfig" support smp 2 )

-- 
Best Regards,
Yu Rong Tan

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Qemu-devel] Does QEMU support MIPS SMP2 malta board?
  2013-10-31  3:47 [Qemu-devel] Does QEMU support MIPS SMP2 malta board? Nancy
@ 2013-11-07 16:13 ` Edgar E. Iglesias
  2013-11-15  9:48   ` Nancy
  0 siblings, 1 reply; 5+ messages in thread
From: Edgar E. Iglesias @ 2013-11-07 16:13 UTC (permalink / raw)
  To: Nancy; +Cc: qemu-devel, qemu-discuss

On Thu, Oct 31, 2013 at 11:47:12AM +0800, Nancy wrote:
> Hi,
> 
> Does QEMU support MIPS smp 2 malta board?
> 
> $ qemu-system-mipsel -M malta -kernel vmlinux -initrd  ramfs.cpio.gz \
> -append "console=ttyS0 root=/dev/ram0 maxcpus=2"  -nographic -s \
> -smp 2
>

....

>
> 
> There's no problem while I removing "-smp 2" option. (plus the kernel
> MIPS configure file " malta_defconfig" support smp 2 )


Hi,

Yes it should work.
Can you please try again with -cpu 34Kf?

Cheers,
Edgar

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Qemu-devel] Does QEMU support MIPS SMP2 malta board?
  2013-11-07 16:13 ` Edgar E. Iglesias
@ 2013-11-15  9:48   ` Nancy
  2013-11-15  9:59     ` James Hogan
  2013-11-15 10:37     ` Edgar E. Iglesias
  0 siblings, 2 replies; 5+ messages in thread
From: Nancy @ 2013-11-15  9:48 UTC (permalink / raw)
  To: Edgar E. Iglesias; +Cc: qemu-devel, qemu-discuss

It works with -cpu 34Kf, but why cpuinfo display MIPS 34Kc?
I notes the smp based on kvm implement, but there do not have kvm
implement under target-mips? how this smp implement? Is there any
document record the QEMU MIPS smp internal?

Does QEMU for MIPS target support FPU, SIMD instruction?

cat /proc/cpuinfo
system type        : MIPS Malta
machine            : Unknown
processor        : 0
cpu model        : MIPS 34Kc V0.0  FPU V0.0
BogoMIPS        : 875.72
wait instruction    : yes
microsecond timers    : yes
tlb_entries        : 16
extra interrupt vector    : yes
hardware watchpoint    : yes, count: 1, address/irw mask: [0x0ff8]
isa            : mips1 mips2 mips32r1 mips32r2
ASEs implemented    : mips16 dsp mt
shadow register sets    : 16
kscratch registers    : 0
core            : 0
VCED exceptions        : not available
VCEI exceptions        : not available

processor        : 1
cpu model        : MIPS 34Kc V0.0  FPU V0.0
BogoMIPS        : 841.31
wait instruction    : yes
microsecond timers    : yes
tlb_entries        : 16
extra interrupt vector    : yes
hardware watchpoint    : yes, count: 1, address/irw mask: [0x0ff8]
isa            : mips1 mips2 mips32r1 mips32r2
ASEs implemented    : mips16 dsp mt
shadow register sets    : 16
kscratch registers    : 0
core            : 1
VCED exceptions        : not available
VCEI exceptions        : not available

On Fri, Nov 8, 2013 at 12:13 AM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> On Thu, Oct 31, 2013 at 11:47:12AM +0800, Nancy wrote:
>> Hi,
>>
>> Does QEMU support MIPS smp 2 malta board?
>>
>> $ qemu-system-mipsel -M malta -kernel vmlinux -initrd  ramfs.cpio.gz \
>> -append "console=ttyS0 root=/dev/ram0 maxcpus=2"  -nographic -s \
>> -smp 2
>>
>
> ....
>
>>
>>
>> There's no problem while I removing "-smp 2" option. (plus the kernel
>> MIPS configure file " malta_defconfig" support smp 2 )
>
>
> Hi,
>
> Yes it should work.
> Can you please try again with -cpu 34Kf?
>
> Cheers,
> Edgar



-- 
Best Regards,
Yu Rong Tan

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Qemu-devel] Does QEMU support MIPS SMP2 malta board?
  2013-11-15  9:48   ` Nancy
@ 2013-11-15  9:59     ` James Hogan
  2013-11-15 10:37     ` Edgar E. Iglesias
  1 sibling, 0 replies; 5+ messages in thread
From: James Hogan @ 2013-11-15  9:59 UTC (permalink / raw)
  To: Nancy; +Cc: Edgar E. Iglesias, qemu-devel, qemu-discuss

Hi Nancy,

On 15/11/13 09:48, Nancy wrote:
> I notes the smp based on kvm implement, but there do not have kvm
> implement under target-mips? how this smp implement? Is there any
> document record the QEMU MIPS smp internal?

The KVM patchset added a binary blob of the CPS bootloader to support
multicore:
https://patchwork.kernel.org/patch/2207161/

I believe it's related to the fact that on most real hardware the reset
vectors of the cores aren't controllable so they all start in the boot
PROM, therefore you need some code there to put the other cores in a
loop waiting to be told to go somewhere by the OS.

Cheers
James

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Qemu-devel] Does QEMU support MIPS SMP2 malta board?
  2013-11-15  9:48   ` Nancy
  2013-11-15  9:59     ` James Hogan
@ 2013-11-15 10:37     ` Edgar E. Iglesias
  1 sibling, 0 replies; 5+ messages in thread
From: Edgar E. Iglesias @ 2013-11-15 10:37 UTC (permalink / raw)
  To: Nancy; +Cc: qemu-devel, qemu-discuss

On Fri, Nov 15, 2013 at 05:48:03PM +0800, Nancy wrote:
> It works with -cpu 34Kf, but why cpuinfo display MIPS 34Kc?

I don't know, maybe Linux doesn't differentiate them? Or qemu has
the wrong prid for the 34Kf?


> I notes the smp based on kvm implement, but there do not have kvm
> implement under target-mips? how this smp implement? Is there any
> document record the QEMU MIPS smp internal?

The emulated (TCG) SMP support implements parts of the MIPS MT ASE.
On malta, -smp is a bit of a missuse, it controls the nr of VPEs and
-smp threads=x controls the nr of TCs.

IIRC the SMTC mechanisms are incomplete, both in the kernel and in
QEMU so for example -smp 2,threads=2 wont work.

Not sure what you mean with "based on KVM" but The TCG support for
MT was added independently and AFAIK before KVM mips was published.

Cheers,
Edgar


> 
> Does QEMU for MIPS target support FPU, SIMD instruction?
> 
> cat /proc/cpuinfo
> system type        : MIPS Malta
> machine            : Unknown
> processor        : 0
> cpu model        : MIPS 34Kc V0.0  FPU V0.0
> BogoMIPS        : 875.72
> wait instruction    : yes
> microsecond timers    : yes
> tlb_entries        : 16
> extra interrupt vector    : yes
> hardware watchpoint    : yes, count: 1, address/irw mask: [0x0ff8]
> isa            : mips1 mips2 mips32r1 mips32r2
> ASEs implemented    : mips16 dsp mt
> shadow register sets    : 16
> kscratch registers    : 0
> core            : 0
> VCED exceptions        : not available
> VCEI exceptions        : not available
> 
> processor        : 1
> cpu model        : MIPS 34Kc V0.0  FPU V0.0
> BogoMIPS        : 841.31
> wait instruction    : yes
> microsecond timers    : yes
> tlb_entries        : 16
> extra interrupt vector    : yes
> hardware watchpoint    : yes, count: 1, address/irw mask: [0x0ff8]
> isa            : mips1 mips2 mips32r1 mips32r2
> ASEs implemented    : mips16 dsp mt
> shadow register sets    : 16
> kscratch registers    : 0
> core            : 1
> VCED exceptions        : not available
> VCEI exceptions        : not available
> 
> On Fri, Nov 8, 2013 at 12:13 AM, Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> > On Thu, Oct 31, 2013 at 11:47:12AM +0800, Nancy wrote:
> >> Hi,
> >>
> >> Does QEMU support MIPS smp 2 malta board?
> >>
> >> $ qemu-system-mipsel -M malta -kernel vmlinux -initrd  ramfs.cpio.gz \
> >> -append "console=ttyS0 root=/dev/ram0 maxcpus=2"  -nographic -s \
> >> -smp 2
> >>
> >
> > ....
> >
> >>
> >>
> >> There's no problem while I removing "-smp 2" option. (plus the kernel
> >> MIPS configure file " malta_defconfig" support smp 2 )
> >
> >
> > Hi,
> >
> > Yes it should work.
> > Can you please try again with -cpu 34Kf?
> >
> > Cheers,
> > Edgar
> 
> 
> 
> -- 
> Best Regards,
> Yu Rong Tan

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2013-11-15 10:38 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2013-10-31  3:47 [Qemu-devel] Does QEMU support MIPS SMP2 malta board? Nancy
2013-11-07 16:13 ` Edgar E. Iglesias
2013-11-15  9:48   ` Nancy
2013-11-15  9:59     ` James Hogan
2013-11-15 10:37     ` Edgar E. Iglesias

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