From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VlJD9-0003NO-LB for qemu-devel@nongnu.org; Tue, 26 Nov 2013 09:02:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VlJCz-0007bN-5P for qemu-devel@nongnu.org; Tue, 26 Nov 2013 09:01:55 -0500 Received: from mx1.redhat.com ([209.132.183.28]:23249) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VlJCy-0007Z6-Se for qemu-devel@nongnu.org; Tue, 26 Nov 2013 09:01:45 -0500 Date: Tue, 26 Nov 2013 16:04:55 +0200 From: "Michael S. Tsirkin" Message-ID: <20131126140455.GD21803@redhat.com> References: <1384775449-6693-1-git-send-email-mst@redhat.com> <1384775449-6693-2-git-send-email-mst@redhat.com> <52945802.2010309@redhat.com> <20131126091014.GA18777@redhat.com> <1385463651.10163.10.camel@nilsson.home.kraxel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1385463651.10163.10.camel@nilsson.home.kraxel.org> Subject: Re: [Qemu-devel] [PULL for-1.8 1/2] pc: disable pci-info List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: Eduardo Habkost , "Jordan Justen (Intel address)" , qemu-devel@nongnu.org, Anthony Liguori , Igor Mammedov , Laszlo Ersek On Tue, Nov 26, 2013 at 12:00:51PM +0100, Gerd Hoffmann wrote: > Hi, > > > I think it's down to other qemu bugs (such as _CRS not covering > > all of PCI memory), we shall just fix them. > > i.e. the attached patch should fixup things. > > cheers, > Gerd > Yes, I think it's a start. Q35 is a bit harder because of the MMIO region. Do we want to tweak end too? There's all kind of stuff there so need to be careful ... > >From a81b8d66e24fd298ce7654d424a378337e6cf132 Mon Sep 17 00:00:00 2001 > From: Gerd Hoffmann > Date: Tue, 26 Nov 2013 11:46:11 +0100 > Subject: [PATCH] piix: fix 32bit pci hole > > Make the 32bit pci hole start at end of ram, so all possible address > space is covered. Of course the firmware can use less than that. > Leaving space unused is no problem, mapping pci bars outside the > hole causes problems though. > > Signed-off-by: Gerd Hoffmann > --- > hw/pci-host/piix.c | 10 +--------- > 1 file changed, 1 insertion(+), 9 deletions(-) > > diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c > index edc974e..1414a2b 100644 > --- a/hw/pci-host/piix.c > +++ b/hw/pci-host/piix.c > @@ -345,15 +345,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, > f->ram_memory = ram_memory; > > i440fx = I440FX_PCI_HOST_BRIDGE(dev); > - /* Set PCI window size the way seabios has always done it. */ > - /* Power of 2 so bios can cover it with a single MTRR */ > - if (ram_size <= 0x80000000) { > - i440fx->pci_info.w32.begin = 0x80000000; > - } else if (ram_size <= 0xc0000000) { > - i440fx->pci_info.w32.begin = 0xc0000000; > - } else { > - i440fx->pci_info.w32.begin = 0xe0000000; > - } > + i440fx->pci_info.w32.begin = ram_size; > > memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space, > pci_hole_start, pci_hole_size); > -- > 1.8.3.1 >