From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47095) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VovXU-0001bH-3t for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:33:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VovXM-00075f-HF for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:33:52 -0500 Received: from mail.skyhub.de ([78.46.96.112]:38553) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VovXM-00075F-8r for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:33:44 -0500 Date: Fri, 6 Dec 2013 14:33:39 +0100 From: Borislav Petkov Message-ID: <20131206133339.GC6694@pd.tnic> References: <1386355976-11732-1-git-send-email-qiaowei.ren@intel.com> <1386355976-11732-2-git-send-email-qiaowei.ren@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1386355976-11732-2-git-send-email-qiaowei.ren@intel.com> Subject: Re: [Qemu-devel] [PATCH 2/3] X86, mpx: Intel MPX definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Qiaowei Ren Cc: Liu Jinsong , kvm@vger.kernel.org, x86@kernel.org, Xudong Hao , linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, Ingo Molnar , "H. Peter Anvin" , Paolo Bonzini , Thomas Gleixner On Sat, Dec 07, 2013 at 02:52:55AM +0800, Qiaowei Ren wrote: > > Signed-off-by: Qiaowei Ren > Signed-off-by: Xudong Hao > Signed-off-by: Liu Jinsong > --- > arch/x86/include/asm/cpufeature.h | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) This patch should probably be merged with the next one... > > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h > index d3f5c63..6c2738d 100644 > --- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -216,6 +216,7 @@ > #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ > #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ > #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ > +#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */ > #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ > #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ > #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ > @@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32]; > #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) > #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) > #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) > +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX) ... and we're trying to not have more of those macros so people should be simply using boot_cpu_has(X86_FEATURE_YYY). -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. --