From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vovjv-0007Cm-Bk for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:46:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vovjp-0002Bb-Gs for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:46:42 -0500 Received: from mail.skyhub.de ([78.46.96.112]:59445) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vovjp-0002BX-3v for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:46:37 -0500 Date: Fri, 6 Dec 2013 14:46:31 +0100 From: Borislav Petkov Message-ID: <20131206134631.GD6694@pd.tnic> References: <1386355976-11732-1-git-send-email-qiaowei.ren@intel.com> <1386355976-11732-3-git-send-email-qiaowei.ren@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1386355976-11732-3-git-send-email-qiaowei.ren@intel.com> Subject: Re: [Qemu-devel] [PATCH 3/3] X86, mpx: Intel MPX xstate feature definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Qiaowei Ren Cc: Liu Jinsong , kvm@vger.kernel.org, x86@kernel.org, Xudong Hao , linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, Ingo Molnar , "H. Peter Anvin" , Paolo Bonzini , Thomas Gleixner On Sat, Dec 07, 2013 at 02:52:56AM +0800, Qiaowei Ren wrote: Commit message please. > Signed-off-by: Qiaowei Ren > Signed-off-by: Xudong Hao > Signed-off-by: Liu Jinsong > --- > arch/x86/include/asm/processor.h | 23 +++++++++++++++++++++++ > arch/x86/include/asm/xsave.h | 6 +++++- > 2 files changed, 28 insertions(+), 1 deletions(-) > > diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h > index 987c75e..43be6f6 100644 > --- a/arch/x86/include/asm/processor.h > +++ b/arch/x86/include/asm/processor.h > @@ -370,6 +370,26 @@ struct ymmh_struct { > u32 ymmh_space[64]; > }; > > +struct lwp_struct { > + u64 lwpcb_addr; > + u32 flags; > + u32 buf_head_offset; > + u64 buf_base; > + u32 buf_size; > + u32 filters; > + u64 saved_event_record[4]; > + u32 event_counter[16]; > +}; > + > +struct bndregs_struct { > + u64 bndregs[8]; > +} __packed; > + > +struct bndcsr_struct { > + u64 cfg_reg_u; > + u64 status_reg; > +} __packed; > + > struct xsave_hdr_struct { > u64 xstate_bv; > u64 reserved1[2]; > @@ -380,6 +400,9 @@ struct xsave_struct { > struct i387_fxsave_struct i387; > struct xsave_hdr_struct xsave_hdr; > struct ymmh_struct ymmh; > + struct lwp_struct lwp; I'm guessing this and the struct lwp_struct above is being added so that you can have the LWP XSAVE area size? If so, you don't need it: LWP XSAVE area is 128 bytes at offset 832 according to my manuals so I'd guess having a u8 lwp_area[128] should be fine. > + struct bndregs_struct bndregs; > + struct bndcsr_struct bndcsr; > /* new processor state extensions will go here */ > } __attribute__ ((packed, aligned (64))); > > diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h > index 0415cda..5cd9de3 100644 > --- a/arch/x86/include/asm/xsave.h > +++ b/arch/x86/include/asm/xsave.h > @@ -9,6 +9,8 @@ > #define XSTATE_FP 0x1 > #define XSTATE_SSE 0x2 > #define XSTATE_YMM 0x4 > +#define XSTATE_BNDREGS 0x8 > +#define XSTATE_BNDCSR 0x10 > > #define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE) > > @@ -20,10 +22,12 @@ > #define XSAVE_YMM_SIZE 256 > #define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET) > > +#define XSTATE_FLEXIBLE (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) What's the use of that macro if it is used only once? > +#define XSTATE_EAGER (XSTATE_BNDREGS | XSTATE_BNDCSR) > /* > * These are the features that the OS can handle currently. > */ > -#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) > +#define XCNTXT_MASK (XSTATE_FLEXIBLE | XSTATE_EAGER) > > #ifdef CONFIG_X86_64 > #define REX_PREFIX "0x48, " -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. --