From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32944) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqR16-0001KB-CW for qemu-devel@nongnu.org; Tue, 10 Dec 2013 12:22:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VqR0v-0007Y9-PE for qemu-devel@nongnu.org; Tue, 10 Dec 2013 12:22:40 -0500 Received: from mx1.redhat.com ([209.132.183.28]:13187) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqR0v-0007Y0-G6 for qemu-devel@nongnu.org; Tue, 10 Dec 2013 12:22:29 -0500 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id rBAHMSck026216 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 10 Dec 2013 12:22:28 -0500 Date: Tue, 10 Dec 2013 13:05:42 -0200 From: Marcelo Tosatti Message-ID: <20131210150542.GA27998@amt.cnet> References: <1385401393-14291-1-git-send-email-pbonzini@redhat.com> <20131128102652.GA24261@redhat.com> <52A714AC.3050703@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <52A714AC.3050703@redhat.com> Subject: Re: [Qemu-devel] [PATCH rebased for-1.8] i386: pc: align gpa<->hpa on 1GB boundary (v6) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: qemu-devel@nongnu.org, "Michael S. Tsirkin" On Tue, Dec 10, 2013 at 02:18:36PM +0100, Paolo Bonzini wrote: > Il 28/11/2013 11:26, Michael S. Tsirkin ha scritto: > > On Mon, Nov 25, 2013 at 06:43:13PM +0100, Paolo Bonzini wrote: > >> v2: condition enablement of new mapping to new machine types (Paolo) > >> v3: fix changelog > >> v4: rebase > >> v5: ensure alignment of piecetwo on 2MB GPA (Igor) > >> do not register zero-sized piece-one (Igor) > >> v6: fix memory leak (Igor) > >> fix integer overflow (Igor) > >> > >> ---- > >> > >> Align guest physical address and host physical address > >> beyond guest 4GB on a 1GB boundary. > >> > >> Otherwise 1GB TLBs cannot be cached for the range. > >> > >> Signed-off-by: Marcelo Tosatti > >> [Reorganize code, keep same logic. - Paolo] > >> Signed-off-by: Paolo Bonzini > >> --- > > > > Applied, thanks. > > As discussed offlist, I'm not sure anymore that this is the right > approach to the problem. No doubt it is very clever, in that it is > absolutely transparent to the guest. However, the non-contiguous > mapping of ram_addr_t makes it more complex to associate the right NUMA > policy to the ranges. Please explain what is the difference, and why the complexity does not exist with non-contiguous mapping of ram_addr_t. > If we could make a small guset visible change, it would be simpler to > always make the PCI hole 1GB in size; it is currently 256MB for i440FX > and 1.25GB for q35. We can take a look as soon as the SeaBIOS patches > are in to use QEMU-built ACPI tables. > > Paolo