From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58362) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqUMC-0004Qb-Ox for qemu-devel@nongnu.org; Tue, 10 Dec 2013 15:56:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VqUM4-0006XD-41 for qemu-devel@nongnu.org; Tue, 10 Dec 2013 15:56:40 -0500 Received: from mx1.redhat.com ([209.132.183.28]:45963) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqUM3-0006Wx-Rk for qemu-devel@nongnu.org; Tue, 10 Dec 2013 15:56:32 -0500 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id rBAKuUsI000451 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 10 Dec 2013 15:56:31 -0500 Date: Tue, 10 Dec 2013 23:00:09 +0200 From: "Michael S. Tsirkin" Message-ID: <20131210210009.GA8476@redhat.com> References: <1385401393-14291-1-git-send-email-pbonzini@redhat.com> <20131128102652.GA24261@redhat.com> <52A714AC.3050703@redhat.com> <1386687211.15686.21.camel@nilsson.home.kraxel.org> <52A7377C.7050400@redhat.com> <1386690784.15686.30.camel@nilsson.home.kraxel.org> <52A75364.5060505@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <52A75364.5060505@redhat.com> Subject: Re: [Qemu-devel] [PATCH rebased for-1.8] i386: pc: align gpa<->hpa on 1GB boundary (v6) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laszlo Ersek Cc: Paolo Bonzini , Marcelo Tosatti , Gerd Hoffmann , qemu-devel@nongnu.org On Tue, Dec 10, 2013 at 06:46:12PM +0100, Laszlo Ersek wrote: > On 12/10/13 16:53, Gerd Hoffmann wrote: > > On Di, 2013-12-10 at 16:47 +0100, Laszlo Ersek wrote: > >> On 12/10/13 15:53, Gerd Hoffmann wrote: > >>> Hi, > >>> > >>>> If we could make a small guset visible change, it would be simpler to > >>>> always make the PCI hole 1GB in size; it is currently 256MB for i440FX > >>>> and 1.25GB for q35. > >>> > >>> Easy for i440fx. > >> > >> I think it's going to break OVMF again. > > > > Can't see a reason why it should. > > PCI enumeration in OVMF assigns resources from a window that starts > exactly above the end of below-4gb-memory. For example, in case of a > 2.5GB guest, the frame buffer bar of cirrus can be somewhere just above > 2.5GB. > > If you change the PCI hole in qemu so that it will start at 3GB, always, > then the ACPI tables exported by qemu will also advertise the big mmio > range starting at 3GB. OVMF will pass those tables through to the OS. > Accordingly, the OS will try to access the framebuffer above 3GB, but > OVMF has configured that bar between 2.5GB and 3GB. > > IOW, I think this proposal would undo your [PATCH v2] piix: fix 32bit > pci hole. > > I can of course live with whatever PCI hole as long as it is made > available to OVMF through an easy-to-parse fw_cfg file. Then I can sync > the OVMF enumeration to qemu's preference. > > The fw_cfg file "etc/pci-info" allowed me to do exactly that. But it has > been killed. I'd like it to be resurrected, even if SeaBIOS ignores it. > > Thanks, > Laszlo There's no PCI hole in QEMU. All there is, is RAM split in two chunks: below and above 4G. -- MST