From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Aurelien Jarno <aurelien@aurel32.net>
Cc: qemu-devel@nongnu.org, Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes
Date: Fri, 13 Dec 2013 13:33:53 +1000 [thread overview]
Message-ID: <20131213033353.GB12096@edvb> (raw)
In-Reply-To: <1386893227-18662-1-git-send-email-aurelien@aurel32.net>
On Fri, Dec 13, 2013 at 01:07:06AM +0100, Aurelien Jarno wrote:
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> ---
> target-sh4/translate.c | 167 ++++++++++++++++++++++++++----------------------
> 1 file changed, 90 insertions(+), 77 deletions(-)
>
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 2272eb0..87f532a 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -464,7 +464,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
> - tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
> tcg_temp_free(addr);
> }
> return;
> @@ -472,7 +472,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
> - tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
> tcg_temp_free(addr);
> }
> return;
> @@ -482,14 +482,14 @@ static void _decode_opc(DisasContext * ctx)
> case 0x9000: /* mov.w @(disp,PC),Rn */
> {
> TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);
> - tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
> tcg_temp_free(addr);
> }
> return;
> case 0xd000: /* mov.l @(disp,PC),Rn */
> {
> TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);
> - tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
> tcg_temp_free(addr);
> }
> return;
> @@ -516,28 +516,29 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
> return;
> case 0x2000: /* mov.b Rm,@Rn */
> - tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB);
> return;
> case 0x2001: /* mov.w Rm,@Rn */
> - tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW);
> return;
> case 0x2002: /* mov.l Rm,@Rn */
> - tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
> return;
> case 0x6000: /* mov.b @Rm,Rn */
> - tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
> return;
> case 0x6001: /* mov.w @Rm,Rn */
> - tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
> return;
> case 0x6002: /* mov.l @Rm,Rn */
> - tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
> return;
> case 0x2004: /* mov.b Rm,@-Rn */
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_subi_i32(addr, REG(B11_8), 1);
> - tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
> + /* might cause re-execution */
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB);
> tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */
> tcg_temp_free(addr);
> }
> @@ -546,7 +547,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_subi_i32(addr, REG(B11_8), 2);
> - tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
> tcg_gen_mov_i32(REG(B11_8), addr);
> tcg_temp_free(addr);
> }
> @@ -555,22 +556,22 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_subi_i32(addr, REG(B11_8), 4);
> - tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
> tcg_gen_mov_i32(REG(B11_8), addr);
> }
> return;
> case 0x6004: /* mov.b @Rm+,Rn */
> - tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
> if ( B11_8 != B7_4 )
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
> return;
> case 0x6005: /* mov.w @Rm+,Rn */
> - tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
> if ( B11_8 != B7_4 )
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
> return;
> case 0x6006: /* mov.l @Rm+,Rn */
> - tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
> if ( B11_8 != B7_4 )
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> return;
> @@ -578,7 +579,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> - tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB);
> tcg_temp_free(addr);
> }
> return;
> @@ -586,7 +587,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> - tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
> tcg_temp_free(addr);
> }
> return;
> @@ -594,7 +595,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> - tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
> tcg_temp_free(addr);
> }
> return;
> @@ -602,7 +603,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> - tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_SB);
> tcg_temp_free(addr);
> }
> return;
> @@ -610,7 +611,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> - tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
> tcg_temp_free(addr);
> }
> return;
> @@ -618,7 +619,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> - tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
> tcg_temp_free(addr);
> }
> return;
> @@ -767,9 +768,9 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv arg0, arg1;
> arg0 = tcg_temp_new();
> - tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, MO_TESL);
> arg1 = tcg_temp_new();
> - tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL);
> gen_helper_macl(cpu_env, arg0, arg1);
> tcg_temp_free(arg1);
> tcg_temp_free(arg0);
> @@ -781,9 +782,9 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv arg0, arg1;
> arg0 = tcg_temp_new();
> - tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, MO_TESL);
> arg1 = tcg_temp_new();
> - tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL);
> gen_helper_macw(cpu_env, arg0, arg1);
> tcg_temp_free(arg1);
> tcg_temp_free(arg0);
> @@ -979,11 +980,14 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr_hi = tcg_temp_new();
> int fr = XREG(B7_4);
> tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
> - tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> - tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_gen_qemu_st_i32(cpu_fregs[fr], REG(B11_8),
> + ctx->memidx, MO_TEUL);
> + tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr_hi,
> + ctx->memidx, MO_TEUL);
> tcg_temp_free(addr_hi);
> } else {
> - tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], REG(B11_8),
> + ctx->memidx, MO_TEUL);
> }
> return;
> case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
> @@ -992,11 +996,12 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr_hi = tcg_temp_new();
> int fr = XREG(B11_8);
> tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
> - tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> - tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_TEUL);
> + tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_TEUL);
> tcg_temp_free(addr_hi);
> } else {
> - tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4),
> + ctx->memidx, MO_TEUL);
> }
> return;
> case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
> @@ -1005,12 +1010,13 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr_hi = tcg_temp_new();
> int fr = XREG(B11_8);
> tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
> - tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> - tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_TEUL);
> + tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_TEUL);
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
> tcg_temp_free(addr_hi);
> } else {
> - tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4),
> + ctx->memidx, MO_TEUL);
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> }
> return;
> @@ -1020,16 +1026,17 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new_i32();
> int fr = XREG(B7_4);
> tcg_gen_subi_i32(addr, REG(B11_8), 4);
> - tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEUL);
> tcg_gen_subi_i32(addr, addr, 4);
> - tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(cpu_fregs[fr], addr, ctx->memidx, MO_TEUL);
> tcg_gen_mov_i32(REG(B11_8), addr);
> tcg_temp_free(addr);
> } else {
> TCGv addr;
> addr = tcg_temp_new_i32();
> tcg_gen_subi_i32(addr, REG(B11_8), 4);
> - tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr,
> + ctx->memidx, MO_TEUL);
> tcg_gen_mov_i32(REG(B11_8), addr);
> tcg_temp_free(addr);
> }
> @@ -1041,11 +1048,14 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> if (ctx->flags & FPSCR_SZ) {
> int fr = XREG(B11_8);
> - tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr,
> + ctx->memidx, MO_TEUL);
> tcg_gen_addi_i32(addr, addr, 4);
> - tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr,
> + ctx->memidx, MO_TEUL);
> } else {
> - tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], addr,
> + ctx->memidx, MO_TEUL);
> }
> tcg_temp_free(addr);
> }
> @@ -1057,11 +1067,14 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> if (ctx->flags & FPSCR_SZ) {
> int fr = XREG(B7_4);
> - tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr,
> + ctx->memidx, MO_TEUL);
> tcg_gen_addi_i32(addr, addr, 4);
> - tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr,
> + ctx->memidx, MO_TEUL);
> } else {
> - tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr,
> + ctx->memidx, MO_TEUL);
> }
> tcg_temp_free(addr);
> }
> @@ -1164,9 +1177,9 @@ static void _decode_opc(DisasContext * ctx)
> addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(0), cpu_gbr);
> val = tcg_temp_new();
> - tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
> tcg_gen_andi_i32(val, val, B7_0);
> - tcg_gen_qemu_st8(val, addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
> tcg_temp_free(val);
> tcg_temp_free(addr);
> }
> @@ -1200,7 +1213,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
> - tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB);
> tcg_temp_free(addr);
> }
> return;
> @@ -1208,7 +1221,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
> - tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW);
> tcg_temp_free(addr);
> }
> return;
> @@ -1216,7 +1229,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
> - tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESL);
> tcg_temp_free(addr);
> }
> return;
> @@ -1224,7 +1237,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
> - tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB);
> tcg_temp_free(addr);
> }
> return;
> @@ -1232,7 +1245,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
> - tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW);
> tcg_temp_free(addr);
> }
> return;
> @@ -1240,7 +1253,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
> - tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUL);
> tcg_temp_free(addr);
> }
> return;
> @@ -1248,7 +1261,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
> - tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB);
> tcg_temp_free(addr);
> }
> return;
> @@ -1256,7 +1269,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
> - tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUL);
> tcg_temp_free(addr);
> }
> return;
> @@ -1264,7 +1277,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
> - tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB);
> tcg_temp_free(addr);
> }
> return;
> @@ -1272,7 +1285,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
> - tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW);
> tcg_temp_free(addr);
> }
> return;
> @@ -1288,9 +1301,9 @@ static void _decode_opc(DisasContext * ctx)
> addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(0), cpu_gbr);
> val = tcg_temp_new();
> - tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
> tcg_gen_ori_i32(val, val, B7_0);
> - tcg_gen_qemu_st8(val, addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
> tcg_temp_free(val);
> tcg_temp_free(addr);
> }
> @@ -1318,7 +1331,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv val = tcg_temp_new();
> tcg_gen_add_i32(val, REG(0), cpu_gbr);
> - tcg_gen_qemu_ld8u(val, val, ctx->memidx);
> + tcg_gen_qemu_ld_i32(val, val, ctx->memidx, MO_UB);
> tcg_gen_andi_i32(val, val, B7_0);
> gen_cmp_imm(TCG_COND_EQ, val, 0);
> tcg_temp_free(val);
> @@ -1333,9 +1346,9 @@ static void _decode_opc(DisasContext * ctx)
> addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(0), cpu_gbr);
> val = tcg_temp_new();
> - tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
> tcg_gen_xori_i32(val, val, B7_0);
> - tcg_gen_qemu_st8(val, addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
> tcg_temp_free(val);
> tcg_temp_free(addr);
> }
> @@ -1349,7 +1362,7 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0x4087: /* ldc.l @Rm+,Rn_BANK */
> CHECK_PRIVILEGED
> - tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_ld_i32(ALTREG(B6_4), REG(B11_8), ctx->memidx, MO_TESL);
> tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
> return;
> case 0x0082: /* stc Rm_BANK,Rn */
> @@ -1361,7 +1374,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_subi_i32(addr, REG(B11_8), 4);
> - tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(ALTREG(B6_4), addr, ctx->memidx, MO_TEUL);
> tcg_gen_mov_i32(REG(B11_8), addr);
> tcg_temp_free(addr);
> }
> @@ -1414,7 +1427,7 @@ static void _decode_opc(DisasContext * ctx)
> CHECK_PRIVILEGED
> {
> TCGv val = tcg_temp_new();
> - tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TESL);
> tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
> tcg_temp_free(val);
> tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
> @@ -1430,7 +1443,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_subi_i32(addr, REG(B11_8), 4);
> - tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(cpu_sr, addr, ctx->memidx, MO_TEUL);
> tcg_gen_mov_i32(REG(B11_8), addr);
> tcg_temp_free(addr);
> }
> @@ -1442,7 +1455,7 @@ static void _decode_opc(DisasContext * ctx)
> return; \
> case ldpnum: \
> prechk \
> - tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \
> + tcg_gen_qemu_ld_i32(cpu_##reg, REG(B11_8), ctx->memidx, MO_TESL); \
> tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
> return;
> #define ST(reg,stnum,stpnum,prechk) \
> @@ -1455,7 +1468,7 @@ static void _decode_opc(DisasContext * ctx)
> { \
> TCGv addr = tcg_temp_new(); \
> tcg_gen_subi_i32(addr, REG(B11_8), 4); \
> - tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
> + tcg_gen_qemu_st_i32(cpu_##reg, addr, ctx->memidx, MO_TEUL); \
> tcg_gen_mov_i32(REG(B11_8), addr); \
> tcg_temp_free(addr); \
> } \
> @@ -1483,7 +1496,7 @@ static void _decode_opc(DisasContext * ctx)
> CHECK_FPU_ENABLED
> {
> TCGv addr = tcg_temp_new();
> - tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx, MO_TESL);
> tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
> gen_helper_ld_fpscr(cpu_env, addr);
> tcg_temp_free(addr);
> @@ -1502,7 +1515,7 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
> addr = tcg_temp_new();
> tcg_gen_subi_i32(addr, REG(B11_8), 4);
> - tcg_gen_qemu_st32(val, addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL);
> tcg_gen_mov_i32(REG(B11_8), addr);
> tcg_temp_free(addr);
> tcg_temp_free(val);
> @@ -1511,21 +1524,21 @@ static void _decode_opc(DisasContext * ctx)
> case 0x00c3: /* movca.l R0,@Rm */
> {
> TCGv val = tcg_temp_new();
> - tcg_gen_qemu_ld32u(val, REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL);
> gen_helper_movcal(cpu_env, REG(B11_8), val);
> - tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
> }
> ctx->has_movcal = 1;
> return;
> case 0x40a9:
> /* MOVUA.L @Rm,R0 (Rm) -> R0
> Load non-boundary-aligned data */
> - tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
> return;
> case 0x40e9:
> /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
> Load non-boundary-aligned data */
> - tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
> tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
> return;
> case 0x0029: /* movt Rn */
> @@ -1542,7 +1555,7 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
> tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst);
> tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
> - tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
> gen_set_label(label);
> tcg_gen_movi_i32(cpu_ldst, 0);
> return;
> @@ -1557,7 +1570,7 @@ static void _decode_opc(DisasContext * ctx)
> */
> if (ctx->features & SH_FEATURE_SH4A) {
> tcg_gen_movi_i32(cpu_ldst, 0);
> - tcg_gen_qemu_ld32s(REG(0), REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL);
> tcg_gen_movi_i32(cpu_ldst, 1);
> return;
> } else
> @@ -1655,10 +1668,10 @@ static void _decode_opc(DisasContext * ctx)
> addr = tcg_temp_local_new();
> tcg_gen_mov_i32(addr, REG(B11_8));
> val = tcg_temp_local_new();
> - tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
> + tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
> gen_cmp_imm(TCG_COND_EQ, val, 0);
> tcg_gen_ori_i32(val, val, 0x80);
> - tcg_gen_qemu_st8(val, addr, ctx->memidx);
> + tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
> tcg_temp_free(val);
> tcg_temp_free(addr);
> }
> --
> 1.7.10.4
>
>
next prev parent reply other threads:[~2013-12-13 3:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-13 0:07 [Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes Aurelien Jarno
2013-12-13 3:33 ` Edgar E. Iglesias [this message]
2013-12-13 9:36 ` Alex Bennée
2013-12-13 13:36 ` Aurelien Jarno
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