From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtItZ-0002zb-VH for qemu-devel@nongnu.org; Wed, 18 Dec 2013 10:18:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VtItT-00025Q-M1 for qemu-devel@nongnu.org; Wed, 18 Dec 2013 10:18:45 -0500 Received: from mx1.redhat.com ([209.132.183.28]:9164) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtItT-00025D-Ee for qemu-devel@nongnu.org; Wed, 18 Dec 2013 10:18:39 -0500 Date: Wed, 18 Dec 2013 17:22:27 +0200 From: "Michael S. Tsirkin" Message-ID: <20131218152227.GA21186@redhat.com> References: <1386753670-11238-1-git-send-email-ghammer@redhat.com> <52B1AFC3.1050809@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <52B1AFC3.1050809@redhat.com> Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: Gal Hammer , "seabios@seabios.org" , qemu-devel@nongnu.org On Wed, Dec 18, 2013 at 03:22:59PM +0100, Paolo Bonzini wrote: > Il 11/12/2013 10:21, Gal Hammer ha scritto: > > Fix a bug that was introduced in commit c046e8c4. QEMU fails to > > resume from suspend mode (S3). > >=20 > > Signed-off-by: Gal Hammer > > --- > > hw/acpi/piix4.c | 1 - > > 1 file changed, 1 deletion(-) > >=20 > > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > > index 93849c8..5c736a4 100644 > > --- a/hw/acpi/piix4.c > > +++ b/hw/acpi/piix4.c > > @@ -376,7 +376,6 @@ static void piix4_reset(void *opaque) > > pci_conf[0x5b] =3D 0; > > =20 > > pci_conf[0x40] =3D 0x01; /* PM io base read only bit */ > > - pci_conf[0x80] =3D 0; > > =20 > > if (s->kvm_enabled) { > > /* Mark SMM as already inited (until KVM supports SMM). */ >=20 > Note this is not the APIC base address, that one is 80h on the ISA > bridge (function 0). You're changing the behavior for 80h on the power > management function, which is function 3. The register is "PMBA=E2=80=94= POWER > MANAGEMENT BASE ADDRESS" and it is indeed initialized by SeaBIOS in > piix4_pm_setup (src/fw/pciinit.c). >=20 > Michael, perhaps a part of pci_setup (same file) should run on S3 resum= e? >=20 > Paolo Seems reasonable: either seabios or guest OS must do it, and guest does not seem to. --=20 MST