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From: Christoffer Dall <christoffer.dall@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Patch Tracking <patches@linaro.org>,
	QEMU Developers <qemu-devel@nongnu.org>,
	"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>
Subject: Re: [Qemu-devel] [RFC PATCH v3 01/10] hw: arm_gic: Fix gic_set_irq handling
Date: Wed, 18 Dec 2013 21:49:58 -0800	[thread overview]
Message-ID: <20131219054958.GS5711@cbox> (raw)
In-Reply-To: <CAFEAcA-GyMEVs3PP5B8T4o0=H2eCESZe2MrbPMX=-ZTeJZLUzQ@mail.gmail.com>

On Thu, Nov 28, 2013 at 05:43:54PM +0000, Peter Maydell wrote:
> On 28 November 2013 16:17, Peter Maydell <peter.maydell@linaro.org> wrote:
> > On 19 November 2013 06:18, Christoffer Dall <christoffer.dall@linaro.org> wrote:
> > So I think this is a correct change in the sense that
> > it's fixing the behaviour of this function. However
> > we seem to get our pending behaviour for level triggered
> > interrupts wrong in several places:
> >  * here
> >  * gic_acknowledge_irq (which you fix in a later patch)
> >  * gic_complete_irq, which currently says "enabled
> >    level triggered still-raised interrupts should be
> >    remarked as pending"
> >
> > This feels to me like a cluster of errors which have come
> > from somebody's misreading of the spec and which probably
> > combine to produce a coherent not-too-far-from-correct
> > result, and which we should therefore fix all at once rather
> > than only partially.
> 
> The other possibility is that it's a correct implementation
> of 11MPCore GIC semantics -- the documentation of the
> 11MPCore definitely says that level triggered interrupts
> go from Pending to Active and can't be Active+Pending
> unless software messes with the GIC state. So either
> the docs are actively wrong for 11MPCore or it behaves
> differently from GICv1 and v2 here (my guess would be
> the latter, in which case we need to support both flavours).
> 
A correct implementation?  I don't see how, unless the pending/level
fields are used in some obscure different way for the 11MPCore than for
GICv2.0.  For the 11MPCore, shouldn't it be:

if (level) {
	GIC_SET_LEVEL(irq, cm);
	if (GIC_TEST_TRIGGER || !GIC_TEST_ACTIVE(irq, cm)) {
		GIC_SET_PENDING(irq, target);
	}
} else {
	GIC_CLEAR_LEVEL(irq, cm)
}

and then the acknowledge could should check if the level is high and we
are acking an active interrupt, make it pending instead of inactive?


That being said, we are absolutely sure that support the 11MPCore is
still needed?

I would probably go the route of creating some structs with function
pointers in them for things like the ack or raise etc. which have
different semantics for the two versions and have separate functions to
reduce the branching in each funciton.  What do you think?

-Christoffer

  reply	other threads:[~2013-12-19  5:50 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-19  6:18 [Qemu-devel] [RFC PATCH v3 00/10] Support arm-gic-kvm save/restore Christoffer Dall
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 01/10] hw: arm_gic: Fix gic_set_irq handling Christoffer Dall
2013-11-28 16:17   ` Peter Maydell
2013-11-28 17:43     ` Peter Maydell
2013-12-19  5:49       ` Christoffer Dall [this message]
2013-12-19  9:03         ` Peter Maydell
2013-12-19 13:49           ` Peter Crosthwaite
2013-12-19 13:59             ` Peter Maydell
2013-12-19 14:26               ` Peter Crosthwaite
2013-12-19 14:30                 ` Peter Maydell
2013-12-19  5:44     ` Christoffer Dall
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 02/10] hw: arm_gic: Introduce gic_set_priority function Christoffer Dall
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 03/10] hw: arm_gic: Keep track of SGI sources Christoffer Dall
2013-11-28 17:31   ` Peter Maydell
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 04/10] arm_gic: Support setting/getting binary point reg Christoffer Dall
2013-11-28 17:32   ` Peter Maydell
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 05/10] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER Christoffer Dall
2013-11-28 17:34   ` Peter Maydell
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 06/10] arm_gic: Keep track of GICD_CPENDR and GICD_SPENDR Christoffer Dall
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 07/10] arm_gic: Fix gic_acknowledge_irq pending bit clear Christoffer Dall
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 08/10] vmstate: Add uint32 2D-array support Christoffer Dall
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 09/10] arm_gic: Add GICC_APRn state to the GICState Christoffer Dall
2013-11-28 17:50   ` Peter Maydell
2013-11-19  6:18 ` [Qemu-devel] [RFC PATCH v3 10/10] hw: arm_gic_kvm: Add KVM VGIC save/restore logic Christoffer Dall
2013-11-28 17:55   ` Peter Maydell

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