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From: Christoffer Dall <christoffer.dall@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Patch Tracking <patches@linaro.org>,
	QEMU Developers <qemu-devel@nongnu.org>,
	"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>
Subject: Re: [Qemu-devel] [PATCH v5 4/8] hw: arm_gic: Keep track of SGI sources
Date: Sun, 2 Feb 2014 14:53:38 -0800	[thread overview]
Message-ID: <20140202225338.GA2469@cbox> (raw)
In-Reply-To: <CAFEAcA9D9j73zoL7WZReto6cU3Xxrc=kOE5WUOV0C0GaYQw4mA@mail.gmail.com>

On Fri, Jan 31, 2014 at 06:33:25PM +0000, Peter Maydell wrote:
> On 28 January 2014 20:32, Christoffer Dall <christoffer.dall@linaro.org> wrote:
> > Right now the arm gic emulation doesn't keep track of the source of an
> > SGI (which apparently Linux guests don't use, or they're fine with
> > assuming CPU 0 always).
> >
> > Add the necessary matrix on the GICState structure and maintain the data
> > when setting and clearing the pending state of an IRQ and make the state
> > visible to the guest.
> >
> > Note that we always choose to present the source as the lowest-numbered
> > CPU in case multiple cores have signalled the same SGI number to a core
> > on the system.
> 
> > @@ -531,9 +576,29 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
> >                  GIC_CLEAR_EDGE_TRIGGER(irq + i);
> >              }
> >          }
> > -    } else {
> > +    } else if (offset < 0xf10) {
> >          /* 0xf00 is only handled for 32-bit writes.  */
> >          goto bad_reg;
> > +    } else if (offset < 0xf20) {
> > +        /* GICD_CPENDSGIRn */
> > +        if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
> > +            goto bad_reg;
> > +        }
> > +        irq = (offset - 0xf10);
> > +
> > +        GIC_CLEAR_PENDING(irq, 1 << cpu);
> > +        s->sgi_pending[irq][cpu] &= ~value;
> 
> This doesn't look quite right. If the SGI is pending
> from multiple source CPUs and we use CPENDSGIRn to
> clear the bits corresponding to only some of those
> source CPUs, then the interrupt as a whole should stay
> pending on this (target) CPU. I think this is:
> 
>     s->sgi_pending[irq][cpu] &= ~value;
>     if (s->sgi_pending[irq][cpu] == 0) {
>         GIC_CLEAR_PENDING(irq, 1 << cpu);
>     }

I had this vague feeling that it was too easy when I wrote the code,
nice catch!

> 
> (compare the code in gic_acknowledge_irq())
> 
> If you fix that, then
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> 

Thanks!
-Christoffer

  reply	other threads:[~2014-02-02 22:53 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-01-28 20:32 [Qemu-devel] [PATCH v5 0/8] Support arm-gic-kvm save/restore Christoffer Dall
2014-01-28 20:32 ` [Qemu-devel] [PATCH v5 1/8] arm_gic: Introduce define for GIC_NR_SGIS Christoffer Dall
2014-01-29 12:02   ` Peter Maydell
2014-01-28 20:32 ` [Qemu-devel] [PATCH v5 2/8] arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes Christoffer Dall
2014-01-29 12:03   ` Peter Maydell
2014-01-28 20:32 ` [Qemu-devel] [PATCH v5 3/8] arm_gic: Fix GIC pending behavior Christoffer Dall
2014-01-31 18:09   ` Peter Maydell
2014-02-02 22:53     ` Christoffer Dall
2014-01-28 20:32 ` [Qemu-devel] [PATCH v5 4/8] hw: arm_gic: Keep track of SGI sources Christoffer Dall
2014-01-31 18:33   ` Peter Maydell
2014-02-02 22:53     ` Christoffer Dall [this message]
2014-01-28 20:32 ` [Qemu-devel] [PATCH v5 5/8] arm_gic: Support setting/getting binary point reg Christoffer Dall
2014-01-28 20:32 ` [Qemu-devel] [PATCH v5 6/8] vmstate: Add uint32 2D-array support Christoffer Dall
2014-01-28 20:32 ` [Qemu-devel] [PATCH v5 7/8] arm_gic: Add GICC_APRn state to the GICState Christoffer Dall
2014-01-28 20:32 ` [Qemu-devel] [PATCH v5 8/8] hw: arm_gic_kvm: Add KVM VGIC save/restore logic Christoffer Dall
2014-01-29 13:23 ` [Qemu-devel] [PATCH v5 0/8] Support arm-gic-kvm save/restore Peter Maydell

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