From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59739) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WA5v5-0001jM-QY for qemu-devel@nongnu.org; Sun, 02 Feb 2014 17:53:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WA5uw-0001YX-Dj for qemu-devel@nongnu.org; Sun, 02 Feb 2014 17:53:43 -0500 Received: from mail-pd0-f180.google.com ([209.85.192.180]:58637) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WA5uw-0001YT-8B for qemu-devel@nongnu.org; Sun, 02 Feb 2014 17:53:34 -0500 Received: by mail-pd0-f180.google.com with SMTP id x10so6177669pdj.25 for ; Sun, 02 Feb 2014 14:53:33 -0800 (PST) Date: Sun, 2 Feb 2014 14:53:38 -0800 From: Christoffer Dall Message-ID: <20140202225338.GA2469@cbox> References: <1390941165-2079-1-git-send-email-christoffer.dall@linaro.org> <1390941165-2079-5-git-send-email-christoffer.dall@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v5 4/8] hw: arm_gic: Keep track of SGI sources List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Patch Tracking , QEMU Developers , "kvmarm@lists.cs.columbia.edu" On Fri, Jan 31, 2014 at 06:33:25PM +0000, Peter Maydell wrote: > On 28 January 2014 20:32, Christoffer Dall wrote: > > Right now the arm gic emulation doesn't keep track of the source of an > > SGI (which apparently Linux guests don't use, or they're fine with > > assuming CPU 0 always). > > > > Add the necessary matrix on the GICState structure and maintain the data > > when setting and clearing the pending state of an IRQ and make the state > > visible to the guest. > > > > Note that we always choose to present the source as the lowest-numbered > > CPU in case multiple cores have signalled the same SGI number to a core > > on the system. > > > @@ -531,9 +576,29 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, > > GIC_CLEAR_EDGE_TRIGGER(irq + i); > > } > > } > > - } else { > > + } else if (offset < 0xf10) { > > /* 0xf00 is only handled for 32-bit writes. */ > > goto bad_reg; > > + } else if (offset < 0xf20) { > > + /* GICD_CPENDSGIRn */ > > + if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { > > + goto bad_reg; > > + } > > + irq = (offset - 0xf10); > > + > > + GIC_CLEAR_PENDING(irq, 1 << cpu); > > + s->sgi_pending[irq][cpu] &= ~value; > > This doesn't look quite right. If the SGI is pending > from multiple source CPUs and we use CPENDSGIRn to > clear the bits corresponding to only some of those > source CPUs, then the interrupt as a whole should stay > pending on this (target) CPU. I think this is: > > s->sgi_pending[irq][cpu] &= ~value; > if (s->sgi_pending[irq][cpu] == 0) { > GIC_CLEAR_PENDING(irq, 1 << cpu); > } I had this vague feeling that it was too easy when I wrote the code, nice catch! > > (compare the code in gic_acknowledge_irq()) > > If you fix that, then > Reviewed-by: Peter Maydell > Thanks! -Christoffer