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From: Michael Roth <mdroth@linux.vnet.ibm.com>
To: Aurelien Jarno <aurelien@aurel32.net>, qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	qemu-stable@nongnu.org, Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH v2 1/4] tcg/optimize: fix known-zero bits for right shift ops
Date: Sat, 15 Feb 2014 23:42:53 -0600	[thread overview]
Message-ID: <20140216054253.1350.31556@loki> (raw)
In-Reply-To: <1378747670-25512-2-git-send-email-aurelien@aurel32.net>

Quoting Aurelien Jarno (2013-09-09 12:27:47)
> 32-bit versions of sar and shr ops should not propagate known-zero bits
> from the unused 32 high bits. For sar it could even lead to wrong code
> being generated.
> 
> Cc: Richard Henderson <rth@twiddle.net>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  tcg/optimize.c |   21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)

Ping, looking to pull this in for 1.7.1

> 
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index b29bf25..c539e39 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -730,16 +730,29 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr,
>              mask = temps[args[1]].mask & mask;
>              break;
> 
> -        CASE_OP_32_64(sar):
> +        case INDEX_op_sar_i32:
> +            if (temps[args[2]].state == TCG_TEMP_CONST) {
> +                mask = ((int32_t)temps[args[1]].mask
> +                        >> temps[args[2]].val);
> +            }
> +            break;
> +        case INDEX_op_sar_i64:
>              if (temps[args[2]].state == TCG_TEMP_CONST) {
> -                mask = ((tcg_target_long)temps[args[1]].mask
> +                mask = ((int64_t)temps[args[1]].mask
>                          >> temps[args[2]].val);
>              }
>              break;
> 
> -        CASE_OP_32_64(shr):
> +        case INDEX_op_shr_i32:
>              if (temps[args[2]].state == TCG_TEMP_CONST) {
> -                mask = temps[args[1]].mask >> temps[args[2]].val;
> +                mask = ((uint32_t)temps[args[1]].mask
> +                        >> temps[args[2]].val);
> +            }
> +            break;
> +        case INDEX_op_shr_i64:
> +            if (temps[args[2]].state == TCG_TEMP_CONST) {
> +                mask = ((uint64_t)temps[args[1]].mask
> +                        >> temps[args[2]].val);
>              }
>              break;
> 
> -- 
> 1.7.10.4

  parent reply	other threads:[~2014-02-16  5:43 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-09-09 17:27 [Qemu-devel] [PATCH v2 0/4] tcg/optimize: fixes and improvements Aurelien Jarno
2013-09-09 17:27 ` [Qemu-devel] [PATCH v2 1/4] tcg/optimize: fix known-zero bits for right shift ops Aurelien Jarno
2013-12-06 17:53   ` Richard Henderson
2014-02-16  5:42   ` Michael Roth [this message]
2013-09-09 17:27 ` [Qemu-devel] [PATCH v2 2/4] tcg/optimize: fix known-zero bits optimization Aurelien Jarno
2013-12-06 17:54   ` Richard Henderson
2013-09-09 17:27 ` [Qemu-devel] [PATCH v2 3/4] tcg/optimize: improve known-zero bits for 32-bit ops Aurelien Jarno
2013-12-06 17:54   ` Richard Henderson
2013-09-09 17:27 ` [Qemu-devel] [PATCH v2 4/4] tcg/optimize: add known-zero bits compute for load ops Aurelien Jarno
2013-12-06 17:53   ` Richard Henderson
2013-11-29  9:32 ` [Qemu-devel] [PATCH v2 0/4] tcg/optimize: fixes and improvements Paolo Bonzini

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