From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEuVQ-00009b-2a for qemu-devel@nongnu.org; Sun, 16 Feb 2014 00:43:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WEuVJ-00026H-Ek for qemu-devel@nongnu.org; Sun, 16 Feb 2014 00:43:08 -0500 Received: from e7.ny.us.ibm.com ([32.97.182.137]:50962) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEuVJ-000266-BG for qemu-devel@nongnu.org; Sun, 16 Feb 2014 00:43:01 -0500 Received: from /spool/local by e7.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 16 Feb 2014 00:43:00 -0500 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Roth In-Reply-To: <1378747670-25512-2-git-send-email-aurelien@aurel32.net> References: <1378747670-25512-1-git-send-email-aurelien@aurel32.net> <1378747670-25512-2-git-send-email-aurelien@aurel32.net> Message-ID: <20140216054253.1350.31556@loki> Date: Sat, 15 Feb 2014 23:42:53 -0600 Subject: Re: [Qemu-devel] [PATCH v2 1/4] tcg/optimize: fix known-zero bits for right shift ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , qemu-devel@nongnu.org Cc: Paolo Bonzini , qemu-stable@nongnu.org, Richard Henderson Quoting Aurelien Jarno (2013-09-09 12:27:47) > 32-bit versions of sar and shr ops should not propagate known-zero bits > from the unused 32 high bits. For sar it could even lead to wrong code > being generated. > = > Cc: Richard Henderson > Cc: Paolo Bonzini > Cc: qemu-stable@nongnu.org > Signed-off-by: Aurelien Jarno > --- > tcg/optimize.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) Ping, looking to pull this in for 1.7.1 > = > diff --git a/tcg/optimize.c b/tcg/optimize.c > index b29bf25..c539e39 100644 > --- a/tcg/optimize.c > +++ b/tcg/optimize.c > @@ -730,16 +730,29 @@ static TCGArg *tcg_constant_folding(TCGContext *s, = uint16_t *tcg_opc_ptr, > mask =3D temps[args[1]].mask & mask; > break; > = > - CASE_OP_32_64(sar): > + case INDEX_op_sar_i32: > + if (temps[args[2]].state =3D=3D TCG_TEMP_CONST) { > + mask =3D ((int32_t)temps[args[1]].mask > + >> temps[args[2]].val); > + } > + break; > + case INDEX_op_sar_i64: > if (temps[args[2]].state =3D=3D TCG_TEMP_CONST) { > - mask =3D ((tcg_target_long)temps[args[1]].mask > + mask =3D ((int64_t)temps[args[1]].mask > >> temps[args[2]].val); > } > break; > = > - CASE_OP_32_64(shr): > + case INDEX_op_shr_i32: > if (temps[args[2]].state =3D=3D TCG_TEMP_CONST) { > - mask =3D temps[args[1]].mask >> temps[args[2]].val; > + mask =3D ((uint32_t)temps[args[1]].mask > + >> temps[args[2]].val); > + } > + break; > + case INDEX_op_shr_i64: > + if (temps[args[2]].state =3D=3D TCG_TEMP_CONST) { > + mask =3D ((uint64_t)temps[args[1]].mask > + >> temps[args[2]].val); > } > break; > = > -- = > 1.7.10.4