From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WF3xe-0001Mn-9D for qemu-devel@nongnu.org; Sun, 16 Feb 2014 10:49:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WF3xY-0001FY-7u for qemu-devel@nongnu.org; Sun, 16 Feb 2014 10:48:54 -0500 Received: from mx1.redhat.com ([209.132.183.28]:27171) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WF3xY-0001FM-06 for qemu-devel@nongnu.org; Sun, 16 Feb 2014 10:48:48 -0500 Date: Sun, 16 Feb 2014 17:53:45 +0200 From: "Michael S. Tsirkin" Message-ID: <20140216155345.GH30056@redhat.com> References: <1391777496-3882-1-git-send-email-imammedo@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1391777496-3882-1-git-send-email-imammedo@redhat.com> Subject: Re: [Qemu-devel] [RFC 0/9] generate dynamic _CRS for motherboard resources List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Mammedov Cc: qemu-devel@nongnu.org, anthony@codemonkey.ws, kraxel@redhat.com On Fri, Feb 07, 2014 at 01:51:27PM +0100, Igor Mammedov wrote: > Since introduction of PCIHP, it became problematic to > punch hole in PCI0._CRS statically since PCI hotplug > region size became runtime changeable. What makes it runtime changeable? > So replace static hole punching with dynamically consumed > resources in a child device on PCI0 bus. i.e generate > PNP0C02 device as a child of PCI0 bus at runtime and > consume GPE0, PCI/CPU hotplug IO resources in it instead > of punching holes in static PCI0._CRS. It seems that we are being too exact with IO resources here. Can't we roughly reserve 0xae00 to 0xafff and be done with it? > Tested with Windows XPsp3, Vista, Windows Server 2003, 2008, 2012r2. > > PS: > Series adds several ASL like macros to simplify > code for dynamic generation of AML structures. > > Igor Mammedov (9): > Revert "pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus > resources" > Revert "pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from > PCI bus resources" > Partial revert "pc: ACPI: expose PRST IO range via _CRS" > acpi: replace opencoded opcodes with defines > acpi: add PNP0C02 to PCI0 bus > acpi: consume GPE0 IO resources in PNP0C02 device > acpi: consume CPU hotplug IO resource in PNP0C02 device > pcihp: expose PCI hotplug MMIO base/length as properties of piix4pm > acpi: consume PCIHP IO resource in PNP0C02 device > > hw/acpi/pcihp.c | 28 ++++++ > hw/acpi/piix4.c | 1 + > hw/i386/acpi-build.c | 177 ++++++++++++++++++++++++++++++++++-- > hw/i386/acpi-dsdt-cpu-hotplug.dsl | 11 --- > hw/i386/acpi-dsdt-pci-crs.dsl | 15 +++- > hw/i386/acpi-dsdt.dsl | 39 -------- > hw/i386/q35-acpi-dsdt.dsl | 16 ---- > include/hw/acpi/pcihp.h | 4 + > 8 files changed, 214 insertions(+), 77 deletions(-)