From: Janne Grunau <j@jannau.net>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Alexander Graf" <agraf@suse.de>,
qemu-devel@nongnu.org,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Dirk Mueller" <dmueller@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH 06/16] target-arm: A64: Saturating and narrowing shift ops
Date: Mon, 10 Mar 2014 16:34:31 +0100 [thread overview]
Message-ID: <20140310153431.GW20660@jannau.net> (raw)
In-Reply-To: <1394377867-7115-7-git-send-email-peter.maydell@linaro.org>
On 2014-03-09 15:10:57 +0000, Peter Maydell wrote:
> From: Alex Bennée <alex.bennee@linaro.org>
>
> This implements a the remaining [US][R]SHR[R][2] opcodes which are
there is an extra 'a' and the instructions are [US][Q][R]SHR[U][N][2].
The last '[R]' is at least clearly wrong.
The commit itself looks correct and is tested with libav's test suite.
Janne
next prev parent reply other threads:[~2014-03-10 15:34 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-09 15:10 [Qemu-devel] [PATCH 00/16] A64 Neon patches: sixth set Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 01/16] target-arm: A64: Implement PMULL instruction Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn Peter Maydell
2014-03-13 8:04 ` Laurent Desnogues
2014-03-09 15:10 ` [Qemu-devel] [PATCH 03/16] target-arm: A64: Add last AdvSIMD Integer to FP ops Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc) Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 05/16] target-arm: A64: Add remaining CLS/Z vector ops Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 06/16] target-arm: A64: Saturating and narrowing shift ops Peter Maydell
2014-03-10 15:34 ` Janne Grunau [this message]
2014-03-09 15:10 ` [Qemu-devel] [PATCH 07/16] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 08/16] target-arm: A64: Implement SHLL, SHLL2 Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions Peter Maydell
2014-03-11 13:53 ` Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 10/16] target-arm: A64: Implement FCVTN Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 11/16] target-arm: A64: Implement FCVTL Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 12/16] target-arm: A64: List unsupported shift-imm opcodes Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 13/16] target-arm: A64: Add FRECPX (reciprocal exponent) Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 14/16] target-arm: A64: Implement SRI Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 15/16] target-arm: A64: Implement FRINT* Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 16/16] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder Peter Maydell
2014-03-10 13:24 ` Michael Matz
2014-03-10 13:27 ` Peter Maydell
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