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From: Mark Rutland <mark.rutland@arm.com>
To: Rob Herring <rob.herring@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Anup Patel <anup.patel@linaro.org>,
	"patches@apm.com" <patches@apm.com>,
	"agraf@suse.de" <agraf@suse.de>,
	qemu-devel <qemu-devel@nongnu.org>,
	"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>,
	Christoffer Dall <christoffer.dall@linaro.org>,
	Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Subject: Re: [Qemu-devel] [RFC PATCH 6/7] hw/arm/virt: Use PSCI v0.2 function IDs when kernel supports its
Date: Mon, 17 Mar 2014 10:09:43 +0000	[thread overview]
Message-ID: <20140317100943.GC8070@e106331-lin.cambridge.arm.com> (raw)
In-Reply-To: <CABGGiswXABzSfsX94QHz3+f6CtmdyVtTmODpUhYGOv4G0GQxHg@mail.gmail.com>

On Fri, Mar 14, 2014 at 05:10:34PM +0000, Rob Herring wrote:
> On Fri, Mar 14, 2014 at 5:23 AM, Mark Rutland <mark.rutland@arm.com> wrote:
> > On Fri, Mar 14, 2014 at 06:53:53AM +0000, Pranavkumar Sawargaonkar wrote:
> >> Hi Christoffer,
> >>
> >> On 14 March 2014 09:19, Christoffer Dall <christoffer.dall@linaro.org> wrote:
> >> > On Thu, Feb 27, 2014 at 12:21:07PM +0530, Pranavkumar Sawargaonkar wrote:
> >> >> If we have in-kernel emulation of PSCI v0.2 for KVM ARM/ARM64 then
> >> >> we enable PSCI v0.2 for each VCPU at the time of VCPU init hence we
> >> >> need to provide PSCI v0.2 function IDs via generated DTB.
> >> >>
> >> >> This patch updates generated DTB to have PSCI v0.2 function IDs when
> >> >> we have in-kernel emulation PSCI v0.2 for KVM ARM/ARM64.
> >> >>
> >> >> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
> >> >> Signed-off-by: Anup Patel <anup.patel@linaro.org>
> >> >> ---
> >> >>  hw/arm/virt.c |   25 ++++++++++++++++++++-----
> >> >>  1 file changed, 20 insertions(+), 5 deletions(-)
> >> >>
> >> >> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> >> >> index 517f2fe..a818a80 100644
> >> >> --- a/hw/arm/virt.c
> >> >> +++ b/hw/arm/virt.c
> >> >> @@ -187,11 +187,26 @@ static void create_fdt(VirtBoardInfo *vbi)
> >> >>          qemu_fdt_add_subnode(fdt, "/psci");
> >> >>          qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
> >> >
> >> > was there a decision on the format of the psci 0.2 bindings?
> >> >
> >> > I seem to recall that we should add arm,psci-0.2 or something like that.
> >>
> >> Yes there was a discussion related to that by Mark Rutland and Rob Herring :
> >> http://www.spinics.net/lists/arm-kernel/msg298509.html
> >>
> >> But there is no dt binding added related to psci 0.2 in kernel (I am
> >> not sure about final conclusion of the dt binding to be added). If the
> >> dt binding gets finalized I will definitely revise this patch.
> >> For now I have added old binding only to test the rfc patch (may now
> >> be the right way to do but do not have any option also).
> >
> > I believe Rob and I were happy with PSCI 0.2 IDs being implicit, though
> > for compatibility with existing kernels the IDs in the "arm,psci"
> > binding might also be listed.
> >
> > The only issue was Calxeda highbank/midway systems using pre-release
> > PSCI 0.2 IDs for functions not in the "arm,psci" binding. For those we
> > could allocate a compatilbe string like "calxeda,highbank-psci-0.2" and
> > allow them to be implicit, or just leave them in their current
> > (unsupported) state.
> >
> > Rob, thoughts?
> 
> We need to add "arm,psci-0.2" compatible since "arm,psci" defines all
> the function IDs as required and with 0.2 they are optional.
> 
> For highbank, since firmware and DTB is essentially frozen now, a
> compatible change is not going to happen. It probably means just
> leaving things as is.

Ok.

> 
> For reference, this is what highbank/midway's binding looks like:
> 
>         psci {
>                 compatible      = "arm,psci";
>                 method          = "smc";
>                 cpu_suspend     = <0x84000002>;
>                 cpu_off         = <0x84000004>;
>                 cpu_on          = <0x84000006>;
>                 system_off      = <0x84000100>;
>                 system_reset    = <0x84000101>;
>         };
> 
> I suppose I could just ignore the binding and make highbank reset/off
> functions do custom some PSCI calls. This would mean exposing
> invoke_psci_fn or creating some custom call wrapper.

Is there any good way to tell if a machine is highbank or midway (e.g.
the top-level compatible string)?

We could check for that and if so read the additional values from the
dt. That way highbank and midway get supported but new machines would
still have to follow the IDs from the final release.

This doesn't necessarily have to be documented as an official binding,
it's essentially a workaround for a quirk (though one with a good reason
for existing).

Does that sound reasonable?

Cheers,
Mark.

  reply	other threads:[~2014-03-17 10:10 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1393483868-6151-1-git-send-email-pranavkumar@linaro.org>
2014-02-27  7:11 ` [Qemu-devel] [RFC PATCH 0/7] PSCI v0.2 support for KVM ARM/ARM64 Pranavkumar Sawargaonkar
     [not found] ` <1393483868-6151-2-git-send-email-pranavkumar@linaro.org>
2014-02-27  7:12   ` [Qemu-devel] [RFC PATCH 1/7] linux-headers: Update KVM headers from v3.14-rc3 Pranavkumar Sawargaonkar
     [not found] ` <1393483868-6151-3-git-send-email-pranavkumar@linaro.org>
2014-02-27  7:13   ` [Qemu-devel] [RFC PATCH 2/7] target-arm: Try X-Gene Potenza target type for KVM Aarch64 Pranavkumar Sawargaonkar
     [not found] ` <1393483868-6151-4-git-send-email-pranavkumar@linaro.org>
2014-02-27  7:14   ` [Qemu-devel] [RFC PATCH 3/7] target-arm: Handle exit reason KVM_EXIT_SYSTEM_EVENT Pranavkumar Sawargaonkar
     [not found]   ` <20140314034348.GE24808@cbox>
2014-03-17 19:34     ` Peter Maydell
     [not found] ` <1393483868-6151-5-git-send-email-pranavkumar@linaro.org>
2014-02-27  7:15   ` [Qemu-devel] [RFC PATCH 4/7] target-arm: Provide PSCI v0.2 constants to generic QEMU code Pranavkumar Sawargaonkar
     [not found] ` <1393483868-6151-6-git-send-email-pranavkumar@linaro.org>
2014-02-27  7:16   ` [Qemu-devel] [RFC PATCH 5/7] target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possible Pranavkumar Sawargaonkar
2014-03-17 19:35     ` Peter Maydell
2014-03-17 22:48       ` Christoffer Dall
     [not found] ` <1393483868-6151-7-git-send-email-pranavkumar@linaro.org>
2014-02-27  7:16   ` [Qemu-devel] [RFC PATCH 6/7] hw/arm/virt: Use PSCI v0.2 function IDs when kernel supports its Pranavkumar Sawargaonkar
     [not found]   ` <20140314034926.GF24808@cbox>
2014-03-14  6:53     ` Pranavkumar Sawargaonkar
2014-03-14 10:23       ` Mark Rutland
2014-03-14 17:10         ` Rob Herring
2014-03-17 10:09           ` Mark Rutland [this message]
     [not found] ` <1393483868-6151-8-git-send-email-pranavkumar@linaro.org>
2014-02-27  7:17   ` [Qemu-devel] [RFC PATCH 7/7] target-arm: Hacky implementation of kvm_arch_reset_vcpu() for KVM ARM64 Pranavkumar Sawargaonkar
     [not found]   ` <CAFEAcA9VcpVS_FJKYruCaWB=jr9unkor1aAzAAJX_GLC0LBouw@mail.gmail.com>
2014-02-27 10:35     ` Pranavkumar Sawargaonkar
2014-02-27 11:26       ` Peter Maydell
2014-03-14  3:51       ` Christoffer Dall
2014-03-14  6:58         ` Pranavkumar Sawargaonkar

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