From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WR8y9-0001Rp-Bf for qemu-devel@nongnu.org; Fri, 21 Mar 2014 19:35:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WR8y8-0007xK-N0 for qemu-devel@nongnu.org; Fri, 21 Mar 2014 19:35:21 -0400 Received: from b.painless.aa.net.uk ([2001:8b0:0:30::51bb:1e34]:44854) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WR8y8-0007vm-Hv for qemu-devel@nongnu.org; Fri, 21 Mar 2014 19:35:20 -0400 Received: from c.d.4.9.3.7.0.e.4.f.f.e.9.9.d.4.9.0.3.d.f.7.a.c.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:ca7f:d309:4d99:eff4:e073:94dc] helo=athena.zubnet.me.uk) by b.painless.aa.net.uk with esmtps (TLSv1:AES128-SHA:128) (Exim 4.72) (envelope-from ) id 1WR8y1-0005qD-67 for qemu-devel@nongnu.org; Fri, 21 Mar 2014 23:35:14 +0000 Received: from sdb by athena.zubnet.me.uk with local (Exim 4.82) (envelope-from ) id 1WR8y0-0003c6-II for qemu-devel@nongnu.org; Fri, 21 Mar 2014 23:35:12 +0000 Date: Fri, 21 Mar 2014 23:35:12 +0000 From: Stuart Brady Message-ID: <20140321233512.GA12223@zubnet.me.uk> References: <1395081476-6038-1-git-send-email-rth@twiddle.net> <1395081476-6038-3-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1395081476-6038-3-git-send-email-rth@twiddle.net> Subject: Re: [Qemu-devel] [PATCH 02/14] tcg: Add INDEX_op_trunc_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Mon, Mar 17, 2014 at 11:37:44AM -0700, Richard Henderson wrote: > diff --git a/tcg/README b/tcg/README > index f178212..160cbe8 100644 > --- a/tcg/README > +++ b/tcg/README > @@ -306,6 +306,11 @@ This operation would be equivalent to > > dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00) > > +* trunc_i32 t0, t1, pos > + > +For 64-bit hosts only, right shift the 64-bit input T1 by POS and > +truncate to 32-bit output T0. Depending on the host, this may be > +a simple mov/shift, or may require additional canonicalization. Surely trunc_rshift_i64_i32, which is used elsewhere in this patch? ... or trunc_shr_i64_i32 as we use 'shr' for the existing shift-right op. Cheers, Stuart