From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42672) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WTVUq-0003vG-EH for qemu-devel@nongnu.org; Fri, 28 Mar 2014 08:03:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WTVUg-0001Eo-Jm for qemu-devel@nongnu.org; Fri, 28 Mar 2014 08:02:52 -0400 Received: from e06smtp11.uk.ibm.com ([195.75.94.107]:57304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WTVUg-0001AH-9G for qemu-devel@nongnu.org; Fri, 28 Mar 2014 08:02:42 -0400 Received: from /spool/local by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 28 Mar 2014 12:02:39 -0000 Date: Fri, 28 Mar 2014 13:02:33 +0100 From: Thomas Huth Message-ID: <20140328130233.2b6e8a3e@oc7435384737.ibm.com> In-Reply-To: <6CFA60A9-841A-401E-8A64-B3290F19A54D@suse.de> References: <20140328091659.399643e7@oc7435384737.ibm.com> <6CFA60A9-841A-401E-8A64-B3290F19A54D@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] target-ppc: Problem with mtmsr emulation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: "qemu-ppc@nongnu.org" , "qemu-devel@nongnu.org" On Fri, 28 Mar 2014 18:25:02 +0800 Alexander Graf wrote: > > > > Am 28.03.2014 um 16:16 schrieb Thomas Huth : > > > > > > Hi all! > > > > There seems to be a problem with the emulation of the mtmsr instruction: > > According to the PowerISA spec, chapter Book III-S, the mtmsr opcode > > has a so-called "L" field at bit position 15. Looking at the function > > gen_mtmsr() in target-ppc/translate.c, the bit is taken into account > > since the function checks for ctx->opcode & 0x00010000. > > However, when looking at the GEN_HANDLER definition later in that file: > > > > GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) > > > > you can see that the bit is marked as invalid bit in the 0x001FF801 > > mask, thus if the bit is set, a program exception is generated instead > > of executing the gen_mtmsr() function. > > > > An easy way to fix this for Book III-S is to change the mask to > > 0x001EF801 (just like the mask for mtmsrd), but I am afraid that this > > would break the Book III-E variant of mtmsr, since the embedded version > > does not have this bit defined. Any suggestions how to fix this problem > > in a proper way? > > Please check in the older isa versions whether that bit is declared reserved. > > If it is, we need to make sure we only match it on newer ISA conformance. The oldest ISA version that I've found (version 2.01, from 2003) already contains the L bit, so I assume it's always been there. So it's likely just a Book III-S vs. Book III-E issue. Thomas