From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39638) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WXRnV-0007i7-O5 for qemu-devel@nongnu.org; Tue, 08 Apr 2014 04:54:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WXRnN-00077B-1D for qemu-devel@nongnu.org; Tue, 08 Apr 2014 04:54:25 -0400 Received: from mx1.redhat.com ([209.132.183.28]:20978) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WXRnM-00076L-P0 for qemu-devel@nongnu.org; Tue, 08 Apr 2014 04:54:16 -0400 Date: Tue, 8 Apr 2014 11:54:54 +0300 From: "Michael S. Tsirkin" Message-ID: <20140408085454.GB4880@redhat.com> References: <1396868342-12005-1-git-send-email-marcel.a@redhat.com> <20140407121508.GD16369@redhat.com> <1396874646.5001.76.camel@nilsson.home.kraxel.org> <20140407133415.GB16541@redhat.com> <1396937123.22660.19.camel@nilsson.home.kraxel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1396937123.22660.19.camel@nilsson.home.kraxel.org> Subject: Re: [Qemu-devel] [SeaBIOS] [PATCH] hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: kevin@koconnor.net, seabios@seabios.org, qemu-devel@nongnu.org, Marcel Apfelbaum On Tue, Apr 08, 2014 at 08:05:23AM +0200, Gerd Hoffmann wrote: > On Mo, 2014-04-07 at 16:34 +0300, Michael S. Tsirkin wrote: > > On Mon, Apr 07, 2014 at 02:44:06PM +0200, Gerd Hoffmann wrote: > > > Hi, > > > > > > > > + u8 shpc_cap = pci_find_capability(s->bus_dev, PCI_CAP_ID_SHPC); > > > > > > > One thing I'd do is maybe check that the relevant memory type is > > > > enabled in the bridge (probably just by writing fff to base and reading > > > > it back). > > > > > > > This will give hypervisors an option to avoid wasting resources: > > > > e.g. it's uncommon for express devices to claim IO. > > > > > > I don't think we'll need that for the SHPC bridge. > > > > Why not? > > With typical use cases for the shpc bridge you likely need the io window > anyway. That won't be true after virtio 1.0 is out. > > I'm referring to this text in the bridge specification: > > > > The I/O Base and I/O Limit registers are optional and define an address > > range that is used > > by the bridge to determine when to forward I/O transactions from one > > interface to the > > other. > > If a bridge does not implement an I/O address range, then both the I/O > > Base and I/O > > Limit registers must be implemented as read-only registers that return > > zero when read. If a > > bridge supports an I/O address range, then these registers must be > > initialized by > > configuration software so default states are not specified. > > > > So we should probe bridge for I/O support before wasting I/O resources on it. > > Yes, makes sense from a correctness point of view. So that's all I'm arguing for, for now: let's implement the spec correctly. Whether we should emulate such devices is a separate question. > I suspect you'll have a hard time to find such bridges in the x86 world > though, so I'm not sure it is a good idea to emulate this in qemu. > Guests might not handle it correctly. We'll have to test this. The handling is mostly done by BIOS so I don't expect a lot of problems. > > > For express it indeed makes sense to avoid claiming IO address space. > > > I'd try to find something more automatic though, where you don't need > > > some kind of "disable io for this express port" config option. > > > > Won't same trick as above work? > > Yes, it will work. > > But as we probably want support io on express devices (because it is > used in practice, even though being strongly discouraged in the pci > express specs). So doing it that way would require a config switch on > the qemu side to turn on/off io address space support for express > switches/ports. > > cheers, > Gerd True but I don't see a way around this anyway. At least this way we won't need PV. -- MST