* [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing
@ 2014-04-09 1:52 Peter Crosthwaite
2014-04-09 21:02 ` Beniamino Galvani
0 siblings, 1 reply; 2+ messages in thread
From: Peter Crosthwaite @ 2014-04-09 1:52 UTC (permalink / raw)
To: qemu-devel; +Cc: b.galvani, edgar.iglesias, nathan.rossi, stefanha
From: Nathan Rossi <nathan.rossi@xilinx.com>
Clear the BMCR Reset when writing to registers.
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
[ PC:
* Trivial style fixes to commit message
]
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
hw/net/xilinx_axienet.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 839d97c..0f485a0 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
phy->regs[regnum] = data;
break;
}
+
+ /* Unconditionally clear regs[BMCR][BMCR_RESET] */
+ phy->regs[0] &= ~0x8000;
}
static void
--
1.9.1.1.gbb9f595
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing
2014-04-09 1:52 [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing Peter Crosthwaite
@ 2014-04-09 21:02 ` Beniamino Galvani
0 siblings, 0 replies; 2+ messages in thread
From: Beniamino Galvani @ 2014-04-09 21:02 UTC (permalink / raw)
To: Peter Crosthwaite; +Cc: edgar.iglesias, nathan.rossi, qemu-devel, stefanha
On Tue, Apr 08, 2014 at 06:52:39PM -0700, Peter Crosthwaite wrote:
> From: Nathan Rossi <nathan.rossi@xilinx.com>
>
> Clear the BMCR Reset when writing to registers.
>
> Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
> [ PC:
> * Trivial style fixes to commit message
> ]
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> ---
>
> hw/net/xilinx_axienet.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> index 839d97c..0f485a0 100644
> --- a/hw/net/xilinx_axienet.c
> +++ b/hw/net/xilinx_axienet.c
> @@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
> phy->regs[regnum] = data;
> break;
> }
> +
> + /* Unconditionally clear regs[BMCR][BMCR_RESET] */
> + phy->regs[0] &= ~0x8000;
> }
>
> static void
> --
Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
Ideally we should also restore default values of registers after a
reset, but probably it is not required for the guest to operate
properly.
Beniamino
^ permalink raw reply [flat|nested] 2+ messages in thread
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2014-04-09 1:52 [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing Peter Crosthwaite
2014-04-09 21:02 ` Beniamino Galvani
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