From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhDvh-00022a-Dh for qemu-devel@nongnu.org; Mon, 05 May 2014 04:07:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WhDvW-0005Q9-GB for qemu-devel@nongnu.org; Mon, 05 May 2014 04:07:17 -0400 Received: from e06smtp17.uk.ibm.com ([195.75.94.113]:36424) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhDvW-0005P2-75 for qemu-devel@nongnu.org; Mon, 05 May 2014 04:07:06 -0400 Received: from /spool/local by e06smtp17.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 5 May 2014 09:07:05 +0100 From: Greg Kurz Date: Mon, 05 May 2014 10:07:00 +0200 Message-ID: <20140505080520.25523.44406.stgit@bahia.local> In-Reply-To: <20140505074816.25523.71374.stgit@bahia.local> References: <20140505074816.25523.71374.stgit@bahia.local> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH v3 3/4] target-ppc: ppc can be either endian List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: afaerber@suse.de, agraf@suse.de Cc: peter.maydell@linaro.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR special purpose register to decide the endianness to use when entering interrupt handlers. When running a Linux guest, this provides a hint on the endianness used by the kernel. From a QEMU point of view, the information is needed for legacy virtio support and crash dump support as well. Suggested-by: Benjamin Herrenschmidt Reviewed-by: Alexander Graf Signed-off-by: Greg Kurz --- No changes, resent in case it helps target-ppc/cpu-qom.h | 1 + target-ppc/translate_init.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index 47dc8e6..fdce638 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -76,6 +76,7 @@ typedef struct PowerPCCPUClass { int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx, int mmu_idx); #endif + bool (*interrupts_big_endian)(PowerPCCPU *cpu); } PowerPCCPUClass; /** diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 7f53c33..a27e5a7 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -3102,6 +3102,18 @@ static int check_pow_hid0_74xx (CPUPPCState *env) return 0; } +static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu) +{ + return true; +} + +#ifdef TARGET_PPC64 +static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu) +{ + return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE); +} +#endif + /*****************************************************************************/ /* PowerPC implementations definitions */ @@ -7089,6 +7101,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) POWERPC_FLAG_VSX; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; } POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) @@ -7132,6 +7145,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) POWERPC_FLAG_VSX; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; } static void init_proc_POWER8(CPUPPCState *env) @@ -7189,6 +7203,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) POWERPC_FLAG_VSX; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; } #endif /* defined (TARGET_PPC64) */ @@ -8511,6 +8526,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) pcc->parent_realize = dc->realize; pcc->pvr = CPU_POWERPC_DEFAULT_MASK; pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; dc->realize = ppc_cpu_realizefn; dc->unrealize = ppc_cpu_unrealizefn;