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Date: Sat, 17 May 2014 11:42:56 +1000
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v1 19/22] target-arm: Add storage for
	VBAR_EL2 and 3
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Rob Herring <rob.herring@linaro.org>, Peter Crosthwaite <peter.crosthwaite@xilinx.com>, QEMU Developers <qemu-devel@nongnu.org>, Alexander Graf <agraf@suse.de>, John Williams <john.williams@xilinx.com>, Alex =?iso-8859-1?Q?Benn=E9e?= <alex.bennee@linaro.org>

On Fri, May 16, 2014 at 03:40:22PM +0100, Peter Maydell wrote:
> On 6 May 2014 07:08, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> >  target-arm/cpu.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> > index 34e8f7c..88dfdcb 100644
> > --- a/target-arm/cpu.h
> > +++ b/target-arm/cpu.h
> > @@ -201,7 +201,7 @@ typedef struct CPUARMState {
> >          uint32_t c9_pminten; /* perf monitor interrupt enables */
> >          uint64_t mair_el1;
> >  #define VBAR_EL_IDX(x) (x - 1)
> > -        uint64_t vbar_el[1]; /* vector base address register */
> > +        uint64_t vbar_el[3]; /* vector base address register */
> >          uint32_t c13_fcse; /* FCSE PID.  */
> >          uint64_t contextidr_el1; /* Context ID.  */
> >          uint64_t tpidr_el0; /* User RW Thread register.  */
> > --
> > 1.8.3.2
> 
> You should just fold this into whichever patch causes us to
> start actually accessing vbar_el[] for other ELs.

Agreed, will squash them.

Thanks,
Edgar