From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35248) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WlUGB-0005dt-ML for qemu-devel@nongnu.org; Fri, 16 May 2014 22:22:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WlUG5-00050h-Nc for qemu-devel@nongnu.org; Fri, 16 May 2014 22:22:03 -0400 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]:55765) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WlUG5-00050d-ER for qemu-devel@nongnu.org; Fri, 16 May 2014 22:21:57 -0400 Received: by mail-pa0-f47.google.com with SMTP id lf10so3280822pab.20 for ; Fri, 16 May 2014 19:21:56 -0700 (PDT) Date: Sat, 17 May 2014 12:21:37 +1000 From: "Edgar E. Iglesias" Message-ID: <20140517022137.GH18802@zapo.iiNet> References: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> <1399356506-5609-11-git-send-email-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v1 10/22] target-arm: A64: Introduce arm64_banked_spsr_index() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Rob Herring , Peter Crosthwaite , QEMU Developers , Alexander Graf , John Williams , Alex =?iso-8859-1?Q?Benn=E9e?= On Fri, May 16, 2014 at 03:31:16PM +0100, Peter Maydell wrote: > On 6 May 2014 07:08, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Add arm64_banked_spsr_index(), used to map an Exception Level > > to an index in the baked_spsr array. > > > > Signed-off-by: Edgar E. Iglesias > > --- > > target-arm/helper-a64.c | 5 +++-- > > target-arm/internals.h | 14 ++++++++++++++ > > target-arm/op_helper.c | 3 ++- > > 3 files changed, 19 insertions(+), 3 deletions(-) > > > > diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c > > index 10bd1fc..415efbe 100644 > > --- a/target-arm/helper-a64.c > > +++ b/target-arm/helper-a64.c > > @@ -444,6 +444,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) > > ARMCPU *cpu = ARM_CPU(cs); > > CPUARMState *env = &cpu->env; > > target_ulong addr = env->cp15.vbar_el[VBAR_EL_IDX(1)]; > > + unsigned int spsr_idx = arm64_banked_spsr_index(1); > > int i; > > > > if (arm_current_pl(env) == 0) { > > @@ -488,12 +489,12 @@ void aarch64_cpu_do_interrupt(CPUState *cs) > > } > > > > if (is_a64(env)) { > > - env->banked_spsr[0] = pstate_read(env); > > + env->banked_spsr[spsr_idx] = pstate_read(env); > > env->sp_el[arm_current_pl(env)] = env->xregs[31]; > > env->xregs[31] = env->sp_el[1]; > > env->elr_el[ELR_EL_IDX(1)] = env->pc; > > } else { > > - env->banked_spsr[0] = cpsr_read(env); > > + env->banked_spsr[spsr_idx] = cpsr_read(env); > > if (!env->thumb) { > > env->cp15.esr_el[ESR_EL_IDX(1)] |= 1 << 25; > > } > > This looks bogus -- the function you've added is only > valid if we are taking the exception from AArch64, but we > use the spsr_idx in the from-AArch32 case as well. Good catch, thanks! > > > diff --git a/target-arm/internals.h b/target-arm/internals.h > > index d63a975..7c39946 100644 > > --- a/target-arm/internals.h > > +++ b/target-arm/internals.h > > @@ -75,6 +75,20 @@ static inline void arm_log_exception(int idx) > > */ > > #define GTIMER_SCALE 16 > > > > +/* > > + * For aarch64, map a given EL to an index in the banked_spsr array. > > In comments, "AArch64", please. > > > + */ > > +static inline unsigned int arm64_banked_spsr_index(unsigned int el) > > "aarch64", not "arm64", please. Will fix Cheers, Edgar