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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com,
	rob.herring@linaro.org, aggelerf@ethz.ch, qemu-devel@nongnu.org,
	agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com,
	greg.bellows@linaro.org, pbonzini@redhat.com,
	christoffer.dall@linaro.org, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v1 06/16] target-arm: Add FAR_EL2 and 3
Date: Wed, 4 Jun 2014 04:33:46 +0200	[thread overview]
Message-ID: <20140604023346.GD3378@toto> (raw)
In-Reply-To: <87lhtes35w.fsf@linaro.org>

On Tue, Jun 03, 2014 at 11:22:51AM +0100, Alex Bennée wrote:
> 
> Edgar E. Iglesias writes:
> 
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> >  target-arm/cpu.h    | 2 +-
> >  target-arm/helper.c | 6 ++++++
> >  2 files changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> > index f8ca1da..ef6a95d 100644
> > --- a/target-arm/cpu.h
> > +++ b/target-arm/cpu.h
> > @@ -187,7 +187,7 @@ typedef struct CPUARMState {
> >          uint32_t ifsr_el2; /* Fault status registers.  */
> >          uint64_t esr_el[4];
> >          uint32_t c6_region[8]; /* MPU base/size registers.  */
> > -        uint64_t far_el[2]; /* Fault address registers.  */
> > +        uint64_t far_el[4]; /* Fault address registers.  */
> 
> Ahh my confusion from earlier is now clear. Perhaps the two commits
> should be merged?


Hi,

The point is to have a non-functional diff and then incrementally add
the function to easy bisectability if something breaks. I don't
have a very strong opinion though, so if people insist I can squash.

Cheers,
Edgar

> 
> >          uint64_t par_el1;  /* Translation result. */
> >          uint32_t c9_insn; /* Cache lockdown registers.  */
> >          uint32_t c9_data;
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index da210b9..de5ee40 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -2120,6 +2120,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
> >        .type = ARM_CP_NO_MIGRATE,
> >        .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 1,
> >        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
> > +    { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
> > +      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
> > +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
> >      { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
> >        .type = ARM_CP_NO_MIGRATE,
> >        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
> > @@ -2142,6 +2145,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
> >        .type = ARM_CP_NO_MIGRATE,
> >        .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 1,
> >        .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
> > +    { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
> > +      .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
> > +      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
> >      { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
> >        .type = ARM_CP_NO_MIGRATE,
> >        .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
> 
> -- 
> Alex Bennée

  reply	other threads:[~2014-06-04  2:41 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com>
     [not found] ` <1401434911-26992-15-git-send-email-edgar.iglesias@gmail.com>
2014-06-02  1:30   ` [Qemu-devel] [PATCH v1 14/16] target-arm: A64: Emulate the SMC insn Edgar E. Iglesias
     [not found]   ` <CAOgzsHWqsegcukD8Q45daqbWPSNWoAbcYZcUm1Qe7Wgf=f4FxA@mail.gmail.com>
     [not found]     ` <20140531034925.GP18802@zapo.iiNet>
2014-06-02 16:12       ` Greg Bellows
2014-06-04  2:31         ` Edgar E. Iglesias
     [not found] ` <1401434911-26992-2-git-send-email-edgar.iglesias@gmail.com>
2014-06-02  9:40   ` [Qemu-devel] [PATCH v1 01/16] target-arm: A64: Break out aarch64_save/restore_sp Alex Bennée
     [not found] ` <1401434911-26992-3-git-send-email-edgar.iglesias@gmail.com>
2014-06-02  9:52   ` [Qemu-devel] [PATCH v1 02/16] target-arm: A64: Respect SPSEL in ERET SP restore Alex Bennée
     [not found] ` <1401434911-26992-4-git-send-email-edgar.iglesias@gmail.com>
2014-06-02  9:55   ` [Qemu-devel] [PATCH v1 03/16] target-arm: A64: Respect SPSEL when taking exceptions Alex Bennée
     [not found] ` <1401434911-26992-5-git-send-email-edgar.iglesias@gmail.com>
2014-06-03 10:21   ` [Qemu-devel] [PATCH v1 04/16] target-arm: Make far_el1 an array Alex Bennée
2014-06-03 12:42     ` Greg Bellows
2014-06-03 13:35       ` Alex Bennée
2014-06-03 13:50         ` Greg Bellows
     [not found] ` <1401434911-26992-7-git-send-email-edgar.iglesias@gmail.com>
2014-06-03 10:22   ` [Qemu-devel] [PATCH v1 06/16] target-arm: Add FAR_EL2 and 3 Alex Bennée
2014-06-04  2:33     ` Edgar E. Iglesias [this message]
2014-06-04  7:55       ` Alex Bennée
2014-06-04 15:08         ` Edgar E. Iglesias
     [not found] ` <1401434911-26992-8-git-send-email-edgar.iglesias@gmail.com>
2014-06-03 10:27   ` [Qemu-devel] [PATCH v1 07/16] target-arm: Add HCR_EL2 Alex Bennée
2014-06-04  6:52     ` Edgar E. Iglesias
     [not found] ` <1401434911-26992-9-git-send-email-edgar.iglesias@gmail.com>
2014-06-03 10:30   ` [Qemu-devel] [PATCH v1 08/16] target-arm: Add SCR_EL3 Alex Bennée
     [not found] ` <1401434911-26992-11-git-send-email-edgar.iglesias@gmail.com>
2014-06-03 10:32   ` [Qemu-devel] [PATCH v1 10/16] target-arm: Break out exception masking to a separate func Alex Bennée
2014-06-04  6:55     ` Edgar E. Iglesias
     [not found] ` <1401434911-26992-13-git-send-email-edgar.iglesias@gmail.com>
2014-06-03 10:37   ` [Qemu-devel] [PATCH v1 12/16] target-arm: A64: Correct updates to FAR and ESR on exceptions Alex Bennée
     [not found] ` <1401434911-26992-14-git-send-email-edgar.iglesias@gmail.com>
2014-06-03 10:41   ` [Qemu-devel] [PATCH v1 13/16] target-arm: A64: Emulate the HVC insn Alex Bennée
2014-06-04  7:01     ` Edgar E. Iglesias
2014-06-04  7:26       ` Alex Bennée
2014-06-04 15:03         ` Edgar E. Iglesias
     [not found] ` <1401434911-26992-16-git-send-email-edgar.iglesias@gmail.com>
2014-06-03 10:47   ` [Qemu-devel] [PATCH v1 15/16] target-arm: Add IRQ and FIQ routing to EL2 and 3 Alex Bennée
     [not found] ` <1401434911-26992-12-git-send-email-edgar.iglesias@gmail.com>
2014-06-08 15:51   ` [Qemu-devel] [PATCH v1 11/16] target-arm: Don't take interrupts targeting lower ELs Aggeler  Fabian
2014-06-08 23:43     ` Edgar E. Iglesias
2014-06-10 17:10       ` Aggeler  Fabian
2014-08-01 14:35 ` [Qemu-devel] [PATCH v1 00/16] target-arm: Parts of the AArch64 EL2/3 exception model Peter Maydell
2014-08-01 14:38   ` Peter Maydell
2014-08-05  8:53   ` Edgar E. Iglesias

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