From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51160) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws18z-0003bW-DQ for qemu-devel@nongnu.org; Tue, 03 Jun 2014 22:41:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ws18t-0002Np-CZ for qemu-devel@nongnu.org; Tue, 03 Jun 2014 22:41:37 -0400 Received: from mail-pd0-x234.google.com ([2607:f8b0:400e:c02::234]:46793) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws18t-0002Ng-59 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 22:41:31 -0400 Received: by mail-pd0-f180.google.com with SMTP id y13so5404495pdi.25 for ; Tue, 03 Jun 2014 19:41:30 -0700 (PDT) Date: Wed, 4 Jun 2014 04:33:46 +0200 From: "Edgar E. Iglesias" Message-ID: <20140604023346.GD3378@toto> References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> <1401434911-26992-7-git-send-email-edgar.iglesias@gmail.com> <87lhtes35w.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87lhtes35w.fsf@linaro.org> Subject: Re: [Qemu-devel] [PATCH v1 06/16] target-arm: Add FAR_EL2 and 3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, rob.herring@linaro.org, aggelerf@ethz.ch, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, christoffer.dall@linaro.org, rth@twiddle.net On Tue, Jun 03, 2014 at 11:22:51AM +0100, Alex Bennée wrote: > > Edgar E. Iglesias writes: > > > From: "Edgar E. Iglesias" > > > > Signed-off-by: Edgar E. Iglesias > > --- > > target-arm/cpu.h | 2 +- > > target-arm/helper.c | 6 ++++++ > > 2 files changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index f8ca1da..ef6a95d 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -187,7 +187,7 @@ typedef struct CPUARMState { > > uint32_t ifsr_el2; /* Fault status registers. */ > > uint64_t esr_el[4]; > > uint32_t c6_region[8]; /* MPU base/size registers. */ > > - uint64_t far_el[2]; /* Fault address registers. */ > > + uint64_t far_el[4]; /* Fault address registers. */ > > Ahh my confusion from earlier is now clear. Perhaps the two commits > should be merged? Hi, The point is to have a non-functional diff and then incrementally add the function to easy bisectability if something breaks. I don't have a very strong opinion though, so if people insist I can squash. Cheers, Edgar > > > uint64_t par_el1; /* Translation result. */ > > uint32_t c9_insn; /* Cache lockdown registers. */ > > uint32_t c9_data; > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > index da210b9..de5ee40 100644 > > --- a/target-arm/helper.c > > +++ b/target-arm/helper.c > > @@ -2120,6 +2120,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > > .type = ARM_CP_NO_MIGRATE, > > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 1, > > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, > > + { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > > + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, > > { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, > > .type = ARM_CP_NO_MIGRATE, > > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, > > @@ -2142,6 +2145,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > > .type = ARM_CP_NO_MIGRATE, > > .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 1, > > .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, > > + { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, > > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, > > { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, > > .type = ARM_CP_NO_MIGRATE, > > .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, > > -- > Alex Bennée