From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws5Dy-0006uk-N6 for qemu-devel@nongnu.org; Wed, 04 Jun 2014 03:03:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ws5Ds-0003mY-JM for qemu-devel@nongnu.org; Wed, 04 Jun 2014 03:03:02 -0400 Received: from mail-pb0-x22c.google.com ([2607:f8b0:400e:c01::22c]:46572) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws5Ds-0003mS-Be for qemu-devel@nongnu.org; Wed, 04 Jun 2014 03:02:56 -0400 Received: by mail-pb0-f44.google.com with SMTP id rq2so6580919pbb.17 for ; Wed, 04 Jun 2014 00:02:55 -0700 (PDT) Date: Wed, 4 Jun 2014 08:55:16 +0200 From: "Edgar E. Iglesias" Message-ID: <20140604065516.GF3378@toto> References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> <1401434911-26992-11-git-send-email-edgar.iglesias@gmail.com> <87ha42s2p0.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87ha42s2p0.fsf@linaro.org> Subject: Re: [Qemu-devel] [PATCH v1 10/16] target-arm: Break out exception masking to a separate func List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, rob.herring@linaro.org, aggelerf@ethz.ch, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, christoffer.dall@linaro.org, rth@twiddle.net On Tue, Jun 03, 2014 at 11:32:59AM +0100, Alex Bennée wrote: > > Edgar E. Iglesias writes: > > > From: "Edgar E. Iglesias" > > > > Signed-off-by: Edgar E. Iglesias > > --- > > cpu-exec.c | 5 ++--- > > target-arm/cpu.h | 16 ++++++++++++++++ > > 2 files changed, 18 insertions(+), 3 deletions(-) > > > > diff --git a/cpu-exec.c b/cpu-exec.c > > index 38e5f02..a579ffc 100644 > > --- a/cpu-exec.c > > +++ b/cpu-exec.c > > @@ -478,7 +478,7 @@ int cpu_exec(CPUArchState *env) > > } > > #elif defined(TARGET_ARM) > > if (interrupt_request & CPU_INTERRUPT_FIQ > > - && !(env->daif & PSTATE_F)) { > > + && arm_excp_unmasked(cpu, EXCP_FIQ)) { > > cpu->exception_index = EXCP_FIQ; > > cc->do_interrupt(cpu); > > next_tb = 0; > > @@ -493,8 +493,7 @@ int cpu_exec(CPUArchState *env) > > We avoid this by disabling interrupts when > > pc contains a magic address. */ > > if (interrupt_request & CPU_INTERRUPT_HARD > > - && ((IS_M(env) && env->regs[15] < 0xfffffff0) > > - || !(env->daif & PSTATE_I))) { > > + && arm_excp_unmasked(cpu, EXCP_IRQ)) { > > cpu->exception_index = EXCP_IRQ; > > cc->do_interrupt(cpu); > > next_tb = 0; > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index 5c74adc..9eddcc1 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -1130,6 +1130,22 @@ bool write_cpustate_to_list(ARMCPU *cpu); > > # define TARGET_VIRT_ADDR_SPACE_BITS 32 > > #endif > > > > +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) > > +{ > > + CPUARMState *env = cs->env_ptr; > > + > > + switch (excp_idx) { > > + case EXCP_FIQ: > > + return !(env->daif & PSTATE_F); > > + case EXCP_IRQ: > > + return ((IS_M(env) && env->regs[15] < 0xfffffff0) > > + || !(env->daif & PSTATE_I)); > > + default: > > + assert(0); > > g_assert_not_reached() is clearer about the intent here. Sounds good, will change it. Thanks, Edgar > > > + break; > > + } > > +} > > + > > static inline CPUARMState *cpu_init(const char *cpu_model) > > { > > ARMCPU *cpu = cpu_arm_init(cpu_model); > > -- > Alex Bennée