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From: Aurelien Jarno <aurelien@aurel32.net>
To: Leon Alrae <leon.alrae@imgtec.com>
Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com,
	qemu-devel@nongnu.org, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v2 20/22] mips_malta: update malta's pseudo-bootloader - replace JR with JALR
Date: Thu, 19 Jun 2014 23:27:15 +0200	[thread overview]
Message-ID: <20140619212715.GA14248@ohm.rr44.fr> (raw)
In-Reply-To: <1402499992-64851-21-git-send-email-leon.alrae@imgtec.com>

On Wed, Jun 11, 2014 at 04:19:50PM +0100, Leon Alrae wrote:
> JR has been removed in R6 and now this instruction will cause Reserved
> Instruction Exception. Therefore use JALR with rd=0 which is equivalent to JR.
> 
> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
> ---
>  hw/mips/mips_malta.c |   10 +++++-----
>  1 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index f4a7d47..72071c0 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -694,12 +694,12 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
>      /* Jump to kernel code */
>      stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff));    /* lui ra, high(kernel_entry) */
>      stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff));            /* ori ra, ra, low(kernel_entry) */
> -    stl_p(p++, 0x03e00008);                                      /* jr ra */
> +    stl_p(p++, 0x03e00009);                                      /* jalr ra */
>      stl_p(p++, 0x00000000);                                      /* nop */
>  
>      /* YAMON subroutines */
>      p = (uint32_t *) (base + 0x800);
> -    stl_p(p++, 0x03e00008);                                     /* jr ra */
> +    stl_p(p++, 0x03e00009);                                     /* jalr ra */
>      stl_p(p++, 0x24020000);                                     /* li v0,0 */
>     /* 808 YAMON print */
>      stl_p(p++, 0x03e06821);                                     /* move t5,ra */
> @@ -713,7 +713,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
>      stl_p(p++, 0x00000000);                                     /* nop */
>      stl_p(p++, 0x08000205);                                     /* j 814 */
>      stl_p(p++, 0x00000000);                                     /* nop */
> -    stl_p(p++, 0x01a00008);                                     /* jr t5 */
> +    stl_p(p++, 0x01a00009);                                     /* jalr t5 */
>      stl_p(p++, 0x01602021);                                     /* move a0,t3 */
>      /* 0x83c YAMON print_count */
>      stl_p(p++, 0x03e06821);                                     /* move t5,ra */
> @@ -727,7 +727,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
>      stl_p(p++, 0x258cffff);                                     /* addiu t4,t4,-1 */
>      stl_p(p++, 0x1580fffa);                                     /* bnez t4,84c */
>      stl_p(p++, 0x00000000);                                     /* nop */
> -    stl_p(p++, 0x01a00008);                                     /* jr t5 */
> +    stl_p(p++, 0x01a00009);                                     /* jalr t5 */
>      stl_p(p++, 0x01602021);                                     /* move a0,t3 */
>      /* 0x870 */
>      stl_p(p++, 0x3c08b800);                                     /* lui t0,0xb400 */
> @@ -737,7 +737,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
>      stl_p(p++, 0x31290040);                                     /* andi t1,t1,0x40 */
>      stl_p(p++, 0x1120fffc);                                     /* beqz t1,878 <outch+0x8> */
>      stl_p(p++, 0x00000000);                                     /* nop */
> -    stl_p(p++, 0x03e00008);                                     /* jr ra */
> +    stl_p(p++, 0x03e00009);                                     /* jalr ra */
>      stl_p(p++, 0xa1040000);                                     /* sb a0,0(t0) */
>  

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

  reply	other threads:[~2014-06-19 21:27 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-11 15:19 [Qemu-devel] [PATCH v2 00/22] target-mips: add MIPS64R6 Instruction Set support Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 01/22] target-mips: define ISA_MIPS64R6 Leon Alrae
2014-06-19 21:06   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 02/22] target-mips: signal RI Exception on instructions removed in R6 Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 03/22] target-mips: add SELEQZ and SELNEZ instructions Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 04/22] target-mips: move LL and SC instructions Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 05/22] target-mips: extract decode_opc_special* from decode_opc Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 06/22] target-mips: split decode_opc_special* into *_r6 and *_legacy Leon Alrae
2014-06-19 21:06   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 07/22] target-mips: signal RI Exception on DSP and Loongson instructions Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 08/22] target-mips: move PREF, CACHE, LLD and SCD instructions Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 09/22] target-mips: redefine Integer Multiply and Divide instructions Leon Alrae
2014-06-19 21:06   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 10/22] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 11/22] target-mips: Status.UX/SX/KX enable 32-bit address wrapping Leon Alrae
2014-06-19 21:06   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 12/22] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions Leon Alrae
2014-06-11 16:39   ` Richard Henderson
2014-06-12  8:35     ` Leon Alrae
2014-06-12 14:34       ` Richard Henderson
2014-06-19 21:06   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 13/22] target-mips: add Compact Branches Leon Alrae
2014-06-11 16:52   ` Richard Henderson
2014-06-24 14:03     ` Leon Alrae
2014-06-19 21:06   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 14/22] target-mips: add Addressing and PC-relative instructions Leon Alrae
2014-06-20 20:50   ` Aurelien Jarno
2014-06-24  9:50     ` Leon Alrae
2014-06-24 10:00       ` Peter Maydell
2014-06-24 14:24         ` Richard Henderson
2014-06-24 14:54           ` Peter Maydell
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 15/22] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag Leon Alrae
2014-06-19 21:27   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 16/22] target-mips: add new Floating Point instructions Leon Alrae
2014-06-20 21:14   ` Aurelien Jarno
2014-06-24 12:10     ` Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 17/22] target-mips: add new Floating Point Comparison instructions Leon Alrae
2014-06-20 21:36   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 18/22] target-mips: do not allow Status.FR=0 mode in 64-bit FPU Leon Alrae
2014-06-19 21:27   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 19/22] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions Leon Alrae
2014-06-19 22:22   ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 20/22] mips_malta: update malta's pseudo-bootloader - replace JR with JALR Leon Alrae
2014-06-19 21:27   ` Aurelien Jarno [this message]
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 21/22] target-mips: use pointers referring to appropriate decoding function Leon Alrae
2014-06-19 22:18   ` Aurelien Jarno
2014-06-20  4:09     ` Richard Henderson
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 22/22] target-mips: define a new generic CPU supporting MIPS64R6 Leon Alrae
2014-06-19 22:16   ` Aurelien Jarno
2014-06-24 11:56     ` Leon Alrae

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