Re: [Qemu-devel] [PATCH 09/12] target-mips: save cpu state if instruction can cause an exception

[Aurelien Jarno <aurelien@aurel32.net>]

On Thu, Jun 19, 2014 at 03:45:40PM +0100, Leon Alrae wrote:
> Execution of these instructions can trigger exceptions which are supposed
> to update BadInstr/BadInstrP. Therefore saving cpu state in order capture
> the opcode.

As said in the previous patch, the performance impact would be quite
significant, now generating a few additional move per load store.

> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
> ---
>  target-mips/translate.c |   19 +++++++++++++++++++
>  1 files changed, 19 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index b27d22e..6835504 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -1847,11 +1847,13 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
>      switch (opc) {
>  #if defined(TARGET_MIPS64)
>      case OPC_LWU:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
>          gen_store_gpr(t0, rt);
>          opn = "lwu";
>          break;
>      case OPC_LD:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
>          gen_store_gpr(t0, rt);
>          opn = "ld";
> @@ -1864,6 +1866,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
>          opn = "lld";
>          break;
>      case OPC_LDL:
> +        save_cpu_state(ctx, 0);
>          t1 = tcg_temp_new();
>          tcg_gen_andi_tl(t1, t0, 7);
>  #ifndef TARGET_WORDS_BIGENDIAN
> @@ -1885,6 +1888,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
>          opn = "ldl";
>          break;
>      case OPC_LDR:
> +        save_cpu_state(ctx, 0);
>          t1 = tcg_temp_new();
>          tcg_gen_andi_tl(t1, t0, 7);
>  #ifdef TARGET_WORDS_BIGENDIAN
> @@ -1906,6 +1910,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
>          opn = "ldr";
>          break;
>      case OPC_LDPC:
> +        save_cpu_state(ctx, 0);
>          t1 = tcg_const_tl(pc_relative_pc(ctx));
>          gen_op_addr_add(ctx, t0, t0, t1);
>          tcg_temp_free(t1);
> @@ -1915,6 +1920,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
>          break;
>  #endif
>      case OPC_LWPC:
> +        save_cpu_state(ctx, 0);
>          t1 = tcg_const_tl(pc_relative_pc(ctx));
>          gen_op_addr_add(ctx, t0, t0, t1);
>          tcg_temp_free(t1);
> @@ -1923,31 +1929,37 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
>          opn = "lwpc";
>          break;
>      case OPC_LW:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
>          gen_store_gpr(t0, rt);
>          opn = "lw";
>          break;
>      case OPC_LH:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
>          gen_store_gpr(t0, rt);
>          opn = "lh";
>          break;
>      case OPC_LHU:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW);
>          gen_store_gpr(t0, rt);
>          opn = "lhu";
>          break;
>      case OPC_LB:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
>          gen_store_gpr(t0, rt);
>          opn = "lb";
>          break;
>      case OPC_LBU:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
>          gen_store_gpr(t0, rt);
>          opn = "lbu";
>          break;
>      case OPC_LWL:
> +        save_cpu_state(ctx, 0);
>          t1 = tcg_temp_new();
>          tcg_gen_andi_tl(t1, t0, 3);
>  #ifndef TARGET_WORDS_BIGENDIAN
> @@ -1970,6 +1982,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
>          opn = "lwl";
>          break;
>      case OPC_LWR:
> +        save_cpu_state(ctx, 0);
>          t1 = tcg_temp_new();
>          tcg_gen_andi_tl(t1, t0, 3);
>  #ifdef TARGET_WORDS_BIGENDIAN
> @@ -2017,6 +2030,7 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
>      switch (opc) {
>  #if defined(TARGET_MIPS64)
>      case OPC_SD:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
>          opn = "sd";
>          break;
> @@ -2032,14 +2046,17 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
>          break;
>  #endif
>      case OPC_SW:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
>          opn = "sw";
>          break;
>      case OPC_SH:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW);
>          opn = "sh";
>          break;
>      case OPC_SB:
> +        save_cpu_state(ctx, 0);
>          tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8);
>          opn = "sb";
>          break;
> @@ -8370,6 +8387,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
>      enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP;
>      uint32_t func = ctx->opcode & 0x3f;
>  
> +    save_cpu_state(ctx, 0);
> +
>      switch (op1) {
>      case OPC_ADD_S:
>          {
> -- 
> 1.7.5.4
> 
> 

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net