From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38317) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wz6aV-0007c4-Hm for qemu-devel@nongnu.org; Mon, 23 Jun 2014 11:55:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wz6aO-0002Vm-0m for qemu-devel@nongnu.org; Mon, 23 Jun 2014 11:55:19 -0400 Received: from mx1.redhat.com ([209.132.183.28]:27929) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wz6aN-0002VW-PI for qemu-devel@nongnu.org; Mon, 23 Jun 2014 11:55:11 -0400 Date: Mon, 23 Jun 2014 18:55:35 +0300 From: "Michael S. Tsirkin" Message-ID: <20140623155534.GA18815@redhat.com> References: <1403537391-32514-1-git-send-email-marcel.a@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1403537391-32514-1-git-send-email-marcel.a@redhat.com> Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [SeaBIOS] [PATCH v3] hw/pci: reserve IO and mem for pci express downstream ports with no devices attached List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum Cc: kevin@koconnor.net, seabios@seabios.org, qemu-devel@nongnu.org, kraxel@redhat.com On Mon, Jun 23, 2014 at 06:29:51PM +0300, Marcel Apfelbaum wrote: > Commit c6e298e1f12e0f4ca02b6da5e42919ae055f6830 > hw/pci: reserve IO and mem for pci-2-pci bridges with no devices at= tached >=20 > introduced support for hot-plugging devices behind pci-2-pci bridges. > Extend hotplug support also for pci express downstream ports. >=20 > Signed-off-by: Marcel Apfelbaum Reviewed-by: Michael S. Tsirkin Gerd, is there a plan to do a release for QEMU 2.1? It would be nice to have this patch there. Thanks, > --- > v2 -> v3: > Addressed Michael S. Tsirkin comments: > - Refactored pci_bus_hotplug_support function. > - Removed PCI_EXP_FLAGS_TYPE_SHIFT macro. >=20 > v1 -> v2: > Wrong prefix on first patch. >=20 > src/fw/pciinit.c | 34 ++++++++++++++++++++++++++++++++-- > 1 file changed, 32 insertions(+), 2 deletions(-) >=20 > diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c > index 0ad548f..fd5dfb9 100644 > --- a/src/fw/pciinit.c > +++ b/src/fw/pciinit.c > @@ -636,6 +636,36 @@ pci_region_create_entry(struct pci_bus *bus, struc= t pci_device *dev, > return entry; > } > =20 > +static int pci_bus_hotplug_support(struct pci_bus *bus) > +{ > + u8 pcie_cap =3D pci_find_capability(bus->bus_dev, PCI_CAP_ID_EXP); > + u8 shpc_cap; > + > + if (pcie_cap) { > + u16 pcie_flags =3D pci_config_readw(bus->bus_dev->bdf, > + pcie_cap + PCI_EXP_FLAGS); > + u8 port_type =3D ((pcie_flags & PCI_EXP_FLAGS_TYPE) >> > + (__builtin_ffs(PCI_EXP_FLAGS_TYPE) - 1)); > + u8 downstream_port =3D (port_type =3D=3D PCI_EXP_TYPE_DOWNSTRE= AM) || > + (port_type =3D=3D PCI_EXP_TYPE_ROOT_PORT)= ; > + /* > + * PCI Express SPEC, 7.8.2: > + * Slot Implemented =E2=80=93 When Set, this bit indicates t= hat the Link > + * HwInit associated with this Port is connected to a slot (= as > + * compared to being connected to a system-integrated device= or > + * being disabled). > + * This bit is valid for Downstream Ports. This bit is undef= ined > + * for Upstream Ports. > + */ > + u16 slot_implemented =3D pcie_flags & PCI_EXP_FLAGS_SLOT; > + > + return downstream_port && slot_implemented; > + } > + > + shpc_cap =3D pci_find_capability(bus->bus_dev, PCI_CAP_ID_SHPC); > + return !!shpc_cap; > +} > + > static int pci_bios_check_devices(struct pci_bus *busses) > { > dprintf(1, "PCI: check devices\n"); > @@ -678,7 +708,7 @@ static int pci_bios_check_devices(struct pci_bus *b= usses) > continue; > struct pci_bus *parent =3D &busses[pci_bdf_to_bus(s->bus_dev->= bdf)]; > int type; > - u8 shpc_cap =3D pci_find_capability(s->bus_dev, PCI_CAP_ID_SHP= C); > + int hotplug_support =3D pci_bus_hotplug_support(s); > for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { > u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? > PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; > @@ -687,7 +717,7 @@ static int pci_bios_check_devices(struct pci_bus *b= usses) > if (pci_region_align(&s->r[type]) > align) > align =3D pci_region_align(&s->r[type]); > u64 sum =3D pci_region_sum(&s->r[type]); > - if (!sum && shpc_cap) > + if (!sum && hotplug_support) > sum =3D align; /* reserve min size for hot-plug */ > u64 size =3D ALIGN(sum, align); > int is64 =3D pci_bios_bridge_region_is64(&s->r[type], > --=20 > 1.8.3.1