From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzUbB-0002p7-Bk for qemu-devel@nongnu.org; Tue, 24 Jun 2014 13:33:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WzUb3-0007sJ-0z for qemu-devel@nongnu.org; Tue, 24 Jun 2014 13:33:37 -0400 Received: from e06smtp15.uk.ibm.com ([195.75.94.111]:48546) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzUb2-0007sD-Os for qemu-devel@nongnu.org; Tue, 24 Jun 2014 13:33:28 -0400 Received: from /spool/local by e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 24 Jun 2014 18:33:27 +0100 Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by d06dlp02.portsmouth.uk.ibm.com (Postfix) with ESMTP id 627962190042 for ; Tue, 24 Jun 2014 18:33:12 +0100 (BST) Received: from d06av08.portsmouth.uk.ibm.com (d06av08.portsmouth.uk.ibm.com [9.149.37.249]) by b06cxnps4076.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s5OHXO4c33161424 for ; Tue, 24 Jun 2014 17:33:24 GMT Received: from d06av08.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av08.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s5OHXNok011621 for ; Tue, 24 Jun 2014 11:33:24 -0600 From: Greg Kurz Date: Tue, 24 Jun 2014 19:33:21 +0200 Message-ID: <20140624172636.17522.32936.stgit@bahia.local> In-Reply-To: <20140624151955.17522.62537.stgit@bahia.local> References: <20140624151955.17522.62537.stgit@bahia.local> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH v9 11/22] cpu: introduce CPUClass::virtio_is_big_endian() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Kevin Wolf , Peter Maydell , Stefan Hajnoczi , Juan Quintela , Rusty Russell , Alexander Graf , "Michael S. Tsirkin" , aneesh.kumar@linux.vnet.ibm.com, Anthony Liguori , Amit Shah , Paolo Bonzini , Andreas =?utf-8?q?F=C3=A4rber?= If we want to support targets that can change endianness (modern PPC and ARM for the moment), we need to add a per-CPU class method to be called from the virtio code. The virtio_ prefix in the name is a hint for people to avoid misusage (aka. anywhere but from the virtio code). The default behaviour is to return the compile-time default target endianness. Suggested-by: Peter Maydell Signed-off-by: Greg Kurz --- Changes since v8: - removed the globally visible cpu_virtio_is_big_endian() helper (code is now called directly from virtio, see next patch) include/qom/cpu.h | 1 + qom/cpu.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4b352a2..1aafbf5 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -116,6 +116,7 @@ typedef struct CPUClass { CPUUnassignedAccess do_unassigned_access; void (*do_unaligned_access)(CPUState *cpu, vaddr addr, int is_write, int is_user, uintptr_t retaddr); + bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, diff --git a/qom/cpu.c b/qom/cpu.c index fada2d4..b32dd0a 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -196,6 +196,11 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg) return 0; } +bool target_words_bigendian(void); +static bool cpu_common_virtio_is_big_endian(CPUState *cpu) +{ + return target_words_bigendian(); +} void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags) @@ -334,6 +339,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->write_elf64_note = cpu_common_write_elf64_note; k->gdb_read_register = cpu_common_gdb_read_register; k->gdb_write_register = cpu_common_gdb_write_register; + k->virtio_is_big_endian = cpu_common_virtio_is_big_endian; dc->realize = cpu_common_realizefn; /* * Reason: CPUs still need special care by board code: wiring up