Re: [Qemu-devel] [PATCH 1/4] mips/kvm: Init EBase to correct KSEG0

[Aurelien Jarno <aurelien@aurel32.net>]

On Thu, Jun 26, 2014 at 10:44:22AM +0100, James Hogan wrote:
> The EBase CP0 register is initialised to 0x80000000, however with KVM
> the guest's KSEG0 is at 0x40000000. The incorrect value doesn't get
> passed to KVM yet as KVM doesn't implement the EBase register, however
> we should set it correctly now so as not to break migration/loadvm to a
> future version of QEMU that does support EBase.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  target-mips/translate.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 2f91959ed7b1..d7b8c4dbc81a 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -28,6 +28,7 @@
>  
>  #include "exec/helper-proto.h"
>  #include "exec/helper-gen.h"
> +#include "sysemu/kvm.h"
>  
>  #define MIPS_DEBUG_DISAS 0
>  //#define MIPS_DEBUG_SIGN_EXTENSIONS
> @@ -16076,7 +16077,12 @@ void cpu_state_reset(CPUMIPSState *env)
>      env->CP0_Random = env->tlb->nb_tlb - 1;
>      env->tlb->tlb_in_use = env->tlb->nb_tlb;
>      env->CP0_Wired = 0;
> -    env->CP0_EBase = 0x80000000 | (cs->cpu_index & 0x3FF);
> +    env->CP0_EBase = (cs->cpu_index & 0x3FF);
> +    if (kvm_enabled()) {
> +        env->CP0_EBase |= 0x40000000;
> +    } else {
> +        env->CP0_EBase |= 0x80000000;
> +    }
>      env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
>      /* vectored interrupts not implemented, timer on int 7,
>         no performance counters. */

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net