From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1tFI-0001R5-CU for qemu-devel@nongnu.org; Tue, 01 Jul 2014 04:17:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1tFE-0001Q9-8I for qemu-devel@nongnu.org; Tue, 01 Jul 2014 04:16:56 -0400 Received: from mail-yh0-x235.google.com ([2607:f8b0:4002:c01::235]:60704) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1tFE-0001P8-2B for qemu-devel@nongnu.org; Tue, 01 Jul 2014 04:16:52 -0400 Received: by mail-yh0-f53.google.com with SMTP id b6so5701428yha.40 for ; Tue, 01 Jul 2014 01:16:51 -0700 (PDT) Date: Tue, 1 Jul 2014 18:15:55 +1000 From: "Edgar E. Iglesias" Message-ID: <20140701081555.GI13735@toto> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> <1404169773-20264-3-git-send-email-greg.bellows@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1404169773-20264-3-git-send-email-greg.bellows@linaro.org> Subject: Re: [Qemu-devel] [PATCH v4 02/33] target-arm: move Aarch32 SCR into security reglist List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: greg.bellows@linaro.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Sergey Fedorov , Fabian Aggeler , qemu-devel@nongnu.org, serge.fdrv@gmail.com, christoffer.dall@linaro.org On Mon, Jun 30, 2014 at 06:09:02PM -0500, greg.bellows@linaro.org wrote: > From: Fabian Aggeler > > Define a new ARM CP register info list for the ARMv7 Security Extension > feature. Register that list only for ARM cores with Security Extension/EL3 > support. Moving Aarch32 SCR into Security Extension register group. > > Signed-off-by: Sergey Fedorov > Signed-off-by: Fabian Aggeler > Signed-off-by: Greg Bellows Reviewed-by: Edgar E. Iglesias > > ------------------ > v3 -> v4 > - Renamed security_cp_reginfo to v7_el3_cp_reginfo > - Conditionalized define on whether v7 or v8 were enabled > > Signed-off-by: Greg Bellows > --- > target-arm/helper.c | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 7c4b801..1ea30fe 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -792,9 +792,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > .access = PL1_RW, .writefn = vbar_write, > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), > .resetvalue = 0 }, > - { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), > - .resetvalue = 0, }, > { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, > .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, > @@ -2227,6 +2224,13 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > REGINFO_SENTINEL > }; > > +static const ARMCPRegInfo v7_el3_cp_reginfo[] = { > + { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), > + .resetvalue = 0, }, > + REGINFO_SENTINEL > +}; > + > static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > @@ -2489,7 +2493,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) > } > } > if (arm_feature(env, ARM_FEATURE_EL3)) { > - define_arm_cp_regs(cpu, v8_el3_cp_reginfo); > + if (arm_feature(env, ARM_FEATURE_V8)) { > + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); > + } > + if (arm_feature(env, ARM_FEATURE_V7)) { > + define_arm_cp_regs(cpu, v7_el3_cp_reginfo); > + } > } > if (arm_feature(env, ARM_FEATURE_MPU)) { > /* These are the MPU registers prior to PMSAv6. Any new > -- > 1.8.3.2 >