qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: greg.bellows@linaro.org
Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com,
	Sergey Fedorov <s.fedorov@samsung.com>,
	Fabian Aggeler <aggelerf@ethz.ch>,
	qemu-devel@nongnu.org, serge.fdrv@gmail.com,
	christoffer.dall@linaro.org
Subject: Re: [Qemu-devel] [PATCH v4 04/33] target-arm: add arm_is_secure() function
Date: Tue, 1 Jul 2014 18:17:56 +1000	[thread overview]
Message-ID: <20140701081756.GJ13735@toto> (raw)
In-Reply-To: <1404169773-20264-5-git-send-email-greg.bellows@linaro.org>

On Mon, Jun 30, 2014 at 06:09:04PM -0500, greg.bellows@linaro.org wrote:
> From: Fabian Aggeler <aggelerf@ethz.ch>
> 
> arm_is_secure() function allows to determine CPU security state
> if the CPU implements Security Extensions/EL3.
> arm_is_secure_below_el3() returns true if CPU is in secure state
> below EL3.
> 
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
> ---
>  target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index ffc51f2..aba077b 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -726,6 +726,44 @@ static inline int arm_feature(CPUARMState *env, int feature)
>      return (env->features & (1ULL << feature)) != 0;
>  }
>  
> +
> +/* Return true if exception level below EL3 is in secure state */
> +static inline bool arm_is_secure_below_el3(CPUARMState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> +    if (arm_feature(env, ARM_FEATURE_EL3)) {
> +        return !(env->cp15.scr_el3 & SCR_NS);
> +    } else if (arm_feature(env, ARM_FEATURE_EL2)) {
> +        return false;
> +    } else {
> +        /* IMPDEF: QEMU defaults to non-secure */
> +        return false;
> +    }
> +#else
> +    return false;
> +#endif
> +}

Should we be #ifdefing the entire arm_is_secure_below_el3() as it is
not called from user-only code?



> +
> +/* Return true if the processor is in secure state */
> +static inline bool arm_is_secure(CPUARMState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> +    if (arm_feature(env, ARM_FEATURE_EL3)) {
> +        if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) {
> +            /* CPU currently in Aarch64 state and EL3 */
> +            return true;
> +        } else if (!env->aarch64 &&
> +                (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
> +            /* CPU currently in Aarch32 state and monitor mode */
> +            return true;
> +        }
> +    }
> +    return arm_is_secure_below_el3(env);
> +#else
> +    return false;
> +#endif
> +}
> +
>  /* Return true if the specified exception level is running in AArch64 state. */
>  static inline bool arm_el_is_aa64(CPUARMState *env, int el)
>  {
> -- 
> 1.8.3.2
> 

  reply	other threads:[~2014-07-01  8:19 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-30 23:09 [Qemu-devel] [PATCH v4 00/33] target-arm: add Security Extensions for CPUs greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 01/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions greg.bellows
2014-09-02 16:34   ` Peter Maydell
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 02/33] target-arm: move Aarch32 SCR into security reglist greg.bellows
2014-07-01  8:15   ` Edgar E. Iglesias
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 03/33] target-arm: increase arrays of registers R13 & R14 greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 04/33] target-arm: add arm_is_secure() function greg.bellows
2014-07-01  8:17   ` Edgar E. Iglesias [this message]
2014-07-01 13:51     ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 05/33] target-arm: reject switching to monitor mode greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 06/33] target-arm: make arm_current_pl() return PL3 greg.bellows
2014-08-26 14:29   ` Peter Maydell
2014-08-28 13:53     ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 07/33] target-arm: add non-secure Translation Block flag greg.bellows
2014-07-01  8:19   ` Edgar E. Iglesias
2014-09-02 16:11   ` Peter Maydell
2014-09-02 16:43     ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 08/33] target-arm: A32: Emulate the SMC instruction greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 09/33] target-arm: extend Aarch32 async excp masking greg.bellows
2014-07-01  8:22   ` Edgar E. Iglesias
2014-07-01 13:33     ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 10/33] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 11/33] target-arm: add async excp target_el&mode function greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 12/33] target-arm: use dedicated target_el function greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 13/33] target-arm: implement IRQ/FIQ routing to Monitor mode greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 14/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 15/33] target-arm: add NSACR register greg.bellows
2014-07-07  9:40   ` Aggeler  Fabian
2014-07-07 14:15     ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 16/33] target-arm: add SDER definition greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 17/33] target-arm: add MVBAR support greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 18/33] target-arm: add macros to access banked registers greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 19/33] target-arm: insert Aarch32 cpregs twice into hashtable greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 20/33] target-arm: arrayfying fieldoffset for banking greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 21/33] target-arm: add SCTLR_EL3 and make SCTLR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 22/33] target-arm: make CSSELR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 23/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 24/33] target-arm: add TCR_EL3 and make TTBCR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 25/33] target-arm: make c2_mask and c2_base_mask banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 26/33] target-arm: make DACR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 27/33] target-arm: make IFSR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 28/33] target-arm: make DFSR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 29/33] target-arm: make IFAR/DFAR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 30/33] target-arm: make PAR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 31/33] target-arm: make VBAR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 32/33] target-arm: make c13 cp regs banked (FCSEIDR, ...) greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate CP regs greg.bellows
2014-07-02  9:41 ` [Qemu-devel] [PATCH v4 00/33] target-arm: add Security Extensions for CPUs Aggeler  Fabian
2014-09-05 17:55 ` Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20140701081756.GJ13735@toto \
    --to=edgar.iglesias@gmail.com \
    --cc=aggelerf@ethz.ch \
    --cc=christoffer.dall@linaro.org \
    --cc=greg.bellows@linaro.org \
    --cc=peter.crosthwaite@xilinx.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=s.fedorov@samsung.com \
    --cc=serge.fdrv@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).