From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38817) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X72z6-0007ck-0k for qemu-devel@nongnu.org; Tue, 15 Jul 2014 09:41:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X72z0-0003Zz-Bz for qemu-devel@nongnu.org; Tue, 15 Jul 2014 09:41:31 -0400 Received: from afflict.kos.to ([92.243.29.197]:37172) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X72z0-0003ZZ-6Z for qemu-devel@nongnu.org; Tue, 15 Jul 2014 09:41:26 -0400 Date: Tue, 15 Jul 2014 16:41:25 +0300 From: Riku Voipio Message-ID: <20140715134125.GG607@afflict.kos.to> References: <1405007407-23549-1-git-send-email-alex.bennee@linaro.org> <1405007407-23549-6-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1405007407-23549-6-git-send-email-alex.bennee@linaro.org> Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 05/10] arm/nwfps: replace cpsr_write with set_condition_codes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?utf-8?Q?Benn=C3=A9e?= Cc: Riku Voipio , qemu-devel@nongnu.org On Thu, Jul 10, 2014 at 04:50:02PM +0100, Alex Benn=C3=A9e wrote: > This is a pre-cursor to removing the cpsr_write function completely fro= m > the code base. set_condition_codes() only affects the integer condition > flags. Acked-by: Riku Voipio > Signed-off-by: Alex Benn=C3=A9e >=20 > --- >=20 > v2 > - fix nwfpe set_condition_codes >=20 > diff --git a/linux-user/arm/nwfpe/fpa11.h b/linux-user/arm/nwfpe/fpa11.= h > index bb9ac65..c7883d0 100644 > --- a/linux-user/arm/nwfpe/fpa11.h > +++ b/linux-user/arm/nwfpe/fpa11.h > @@ -108,7 +108,7 @@ static inline void writeRegister(unsigned int x, un= signed int y) > =20 > static inline void writeConditionCodes(unsigned int x) > { > - cpsr_write(user_registers,x,CPSR_NZCV); > + set_condition_codes(user_registers, x); > } > =20 > #define ARM_REG_PC 15 > --=20 > 2.0.1 >=20