From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X730l-0000gW-Fd for qemu-devel@nongnu.org; Tue, 15 Jul 2014 09:43:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X730f-00054H-S6 for qemu-devel@nongnu.org; Tue, 15 Jul 2014 09:43:15 -0400 Received: from afflict.kos.to ([92.243.29.197]:37180) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X730f-000541-JL for qemu-devel@nongnu.org; Tue, 15 Jul 2014 09:43:09 -0400 Date: Tue, 15 Jul 2014 16:43:09 +0300 From: Riku Voipio Message-ID: <20140715134309.GH607@afflict.kos.to> References: <1405007407-23549-1-git-send-email-alex.bennee@linaro.org> <1405007407-23549-8-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1405007407-23549-8-git-send-email-alex.bennee@linaro.org> Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 07/10] target-arm: remove last users of cpsr_write List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?utf-8?Q?Benn=C3=A9e?= Cc: Peter Maydell , Riku Voipio , qemu-devel@nongnu.org On Thu, Jul 10, 2014 at 04:50:04PM +0100, Alex Benn=C3=A9e wrote: > And use the new machinery to to save and restore program state. The old > cpsr_write function did some special handling for mode switches which > has been moved into the helper function. Again for the linux-user part, Acked-by: Riku Voipio > Signed-off-by: Alex Benn=C3=A9e >=20 > --- > v2: > - rebase > - add mask helper function > - checkpatch fixes >=20 > diff --git a/linux-user/main.c b/linux-user/main.c > index 9101541..5f7cc31 100644 > --- a/linux-user/main.c > +++ b/linux-user/main.c > @@ -4184,7 +4184,7 @@ int main(int argc, char **argv, char **envp) > #elif defined(TARGET_ARM) > { > int i; > - cpsr_write(env, regs->uregs[16], 0xffffffff); > + restore_state_from_spsr(env, regs->uregs[16]); > for(i =3D 0; i < 16; i++) { > env->regs[i] =3D regs->uregs[i]; > } > diff --git a/linux-user/signal.c b/linux-user/signal.c > index 9c6727b..b6f9ef4 100644 > --- a/linux-user/signal.c > +++ b/linux-user/signal.c > @@ -1599,38 +1599,39 @@ get_sigframe(struct target_sigaction *ka, CPUAR= MState *regs, int framesize) > =20 > static void > setup_return(CPUARMState *env, struct target_sigaction *ka, > - abi_ulong *rc, abi_ulong frame_addr, int usig, abi_ulong rc_addr= ) > + abi_ulong *rc, abi_ulong frame_addr, int usig, abi_ulong = rc_addr) > { > - abi_ulong handler =3D ka->_sa_handler; > - abi_ulong retcode; > - int thumb =3D handler & 1; > - uint32_t cpsr =3D save_state_to_spsr(env); > + abi_ulong handler =3D ka->_sa_handler; > + abi_ulong retcode; > + int thumb =3D handler & 1; > + uint32_t cpsr =3D save_state_to_spsr(env); > =20 > - cpsr &=3D ~CPSR_IT; > - if (thumb) { > - cpsr |=3D CPSR_T; > - } else { > - cpsr &=3D ~CPSR_T; > - } > + cpsr &=3D ~CPSR_IT; > + if (thumb) { > + cpsr |=3D CPSR_T; > + } else { > + cpsr &=3D ~CPSR_T; > + } > =20 > - if (ka->sa_flags & TARGET_SA_RESTORER) { > - retcode =3D ka->sa_restorer; > - } else { > - unsigned int idx =3D thumb; > + if (ka->sa_flags & TARGET_SA_RESTORER) { > + retcode =3D ka->sa_restorer; > + } else { > + unsigned int idx =3D thumb; > =20 > - if (ka->sa_flags & TARGET_SA_SIGINFO) > - idx +=3D 2; > + if (ka->sa_flags & TARGET_SA_SIGINFO) { > + idx +=3D 2; > + } > =20 > - __put_user(retcodes[idx], rc); > + __put_user(retcodes[idx], rc); > =20 > - retcode =3D rc_addr + thumb; > - } > + retcode =3D rc_addr + thumb; > + } > =20 > - env->regs[0] =3D usig; > - env->regs[13] =3D frame_addr; > - env->regs[14] =3D retcode; > - env->regs[15] =3D handler & (thumb ? ~1 : ~3); > - cpsr_write(env, cpsr, 0xffffffff); > + env->regs[0] =3D usig; > + env->regs[13] =3D frame_addr; > + env->regs[14] =3D retcode; > + env->regs[15] =3D handler & (thumb ? ~1 : ~3); > + restore_state_from_spsr(env, cpsr); > } > =20 > static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *regspace, CPUARMSta= te *env) > @@ -1858,12 +1859,14 @@ restore_sigcontext(CPUARMState *env, struct tar= get_sigcontext *sc) > __get_user(env->regs[15], &sc->arm_pc); > #ifdef TARGET_CONFIG_CPU_32 > __get_user(cpsr, &sc->arm_cpsr); > - cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC); > + restore_state_from_masked_spsr(env, > + (CPSR_USER | CPSR_EXEC), > + cpsr); > #endif > =20 > - err |=3D !valid_user_regs(env); > + err |=3D !valid_user_regs(env); > =20 > - return err; > + return err; > } > =20 > static long do_sigreturn_v1(CPUARMState *env) > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 3f23167..b56f1a8 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -795,6 +795,15 @@ static inline void restore_state_from_spsr(CPUARMS= tate *env, > } > } > =20 > +/* Restore a few masked bits of the program state */ > +static inline void restore_state_from_masked_spsr(CPUARMState *env, > + uint32_t mask, > + uint32_t saved_state= ) > +{ > + uint32_t spsr =3D (save_state_to_spsr(env) & ~mask); > + spsr |=3D (saved_state & mask); > + return restore_state_from_spsr(env, spsr); > +} > =20 > void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); > =20 > diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c > index ec25f30..5e60589 100644 > --- a/target-arm/gdbstub.c > +++ b/target-arm/gdbstub.c > @@ -93,8 +93,12 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) > } > return 4; > case 25: > - /* CPSR */ > - cpsr_write(env, tmp, 0xffffffff); > + /* CPSR > + * FIXME?: as restore_state_from_spsr() doesn't do aarch32 > + * special mode fixups this may break. However GDB doesn't > + * seem to be able to handle tracing over a mode switch anyway > + */ > + restore_state_from_spsr(env, tmp); > return 4; > } > /* Unknown register. */ > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 030bcdd..6d755c0 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2970,68 +2970,6 @@ void arm_cp_reset_ignore(CPUARMState *env, const= ARMCPRegInfo *opaque) > /* Helper coprocessor reset function for do-nothing-on-reset regis= ters */ > } > =20 > -static int bad_mode_switch(CPUARMState *env, int mode) > -{ > - /* Return true if it is not valid for us to switch to > - * this CPU mode (ie all the UNPREDICTABLE cases in > - * the ARM ARM CPSRWriteByInstr pseudocode). > - */ > - switch (mode) { > - case ARM_CPU_MODE_USR: > - case ARM_CPU_MODE_SYS: > - case ARM_CPU_MODE_SVC: > - case ARM_CPU_MODE_ABT: > - case ARM_CPU_MODE_UND: > - case ARM_CPU_MODE_IRQ: > - case ARM_CPU_MODE_FIQ: > - return 0; > - default: > - return 1; > - } > -} > - > -void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) > -{ > - if (mask & CPSR_NZCV) { > - env->ZF =3D (~val) & CPSR_Z; > - env->NF =3D val; > - env->CF =3D (val >> 29) & 1; > - env->VF =3D (val << 3) & 0x80000000; > - } > - if (mask & CPSR_Q) > - env->QF =3D ((val & CPSR_Q) !=3D 0); > - if (mask & CPSR_T) > - env->thumb =3D ((val & CPSR_T) !=3D 0); > - if (mask & CPSR_IT_0_1) { > - env->condexec_bits &=3D ~3; > - env->condexec_bits |=3D (val >> 25) & 3; > - } > - if (mask & CPSR_IT_2_7) { > - env->condexec_bits &=3D 3; > - env->condexec_bits |=3D (val >> 8) & 0xfc; > - } > - if (mask & CPSR_GE) { > - env->GE =3D (val >> 16) & 0xf; > - } > - > - env->daif &=3D ~(CPSR_AIF & mask); > - env->daif |=3D val & CPSR_AIF & mask; > - > - if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { > - if (bad_mode_switch(env, val & CPSR_M)) { > - /* Attempt to switch to an invalid mode: this is UNPREDICT= ABLE. > - * We choose to ignore the attempt and leave the CPSR M fi= eld > - * untouched. > - */ > - mask &=3D ~CPSR_M; > - } else { > - switch_mode(env, val & CPSR_M); > - } > - } > - mask &=3D ~CACHED_CPSR_BITS; > - env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask)= ; > -} > - > /* Sign/zero extend */ > uint32_t HELPER(sxtb16)(uint32_t x) > { > diff --git a/target-arm/kvm32.c b/target-arm/kvm32.c > index 789f52f..39117c7 100644 > --- a/target-arm/kvm32.c > +++ b/target-arm/kvm32.c > @@ -464,7 +464,7 @@ int kvm_arch_get_registers(CPUState *cs) > if (ret) { > return ret; > } > - cpsr_write(env, cpsr, 0xffffffff); > + restore_state_from_spsr(env, cpsr); > =20 > /* Make sure the current mode regs are properly set */ > mode =3D env->uncached_cpsr & CPSR_M; > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 052a4bd..c17bdba 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -261,9 +261,47 @@ uint32_t HELPER(cpsr_read)(CPUARMState *env) > return save_state_to_spsr(env) & ~CPSR_EXEC; > } > =20 > +static int bad_mode_switch(CPUARMState *env, int mode) > +{ > + /* Return true if it is not valid for us to switch to > + * this CPU mode (ie all the UNPREDICTABLE cases in > + * the ARM ARM CPSRWriteByInstr pseudocode). > + */ > + switch (mode) { > + case ARM_CPU_MODE_USR: > + case ARM_CPU_MODE_SYS: > + case ARM_CPU_MODE_SVC: > + case ARM_CPU_MODE_ABT: > + case ARM_CPU_MODE_UND: > + case ARM_CPU_MODE_IRQ: > + case ARM_CPU_MODE_FIQ: > + return 0; > + default: > + return 1; > + } > +} > + > void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) > { > - cpsr_write(env, val, mask); > + uint32_t current_cpsr =3D save_state_to_spsr(env); > + uint32_t new_cpsr; > + > + /* we may be triggering a mode change */ > + if ((current_cpsr ^ val) & mask & CPSR_M) { > + if (bad_mode_switch(env, val & CPSR_M)) { > + /* Attempt to switch to an invalid mode: this is UNPREDICT= ABLE. > + * We choose to ignore the attempt and leave the CPSR M fi= eld > + * untouched. > + */ > + mask &=3D ~CPSR_M; > + } else { > + switch_mode(env, val & CPSR_M); > + } > + } > + > + new_cpsr =3D current_cpsr & ~mask; > + new_cpsr |=3D (val & mask); > + restore_state_from_spsr(env, new_cpsr); > } > =20 > /* Access to user mode registers from privileged modes. */ > --=20 > 2.0.1 >=20