From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58081) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XH7k7-000170-3R for qemu-devel@nongnu.org; Tue, 12 Aug 2014 04:47:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XH7k0-0002d6-VT for qemu-devel@nongnu.org; Tue, 12 Aug 2014 04:47:43 -0400 Received: from mx1.redhat.com ([209.132.183.28]:27886) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XH7k0-0002bO-Nn for qemu-devel@nongnu.org; Tue, 12 Aug 2014 04:47:36 -0400 Date: Tue, 12 Aug 2014 09:47:16 +0100 From: Stefan Hajnoczi Message-ID: <20140812084716.GA19977@stefanha-thinkpad.redhat.com> References: <1407515016-26273-1-git-send-email-mark.cave-ayland@ilande.co.uk> <1407515016-26273-6-git-send-email-mark.cave-ayland@ilande.co.uk> <20140811151223.GF496@stefanha-thinkpad.redhat.com> <53E8E22D.3040001@ilande.co.uk> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="rwEMma7ioTxnRzrJ" Content-Disposition: inline In-Reply-To: <53E8E22D.3040001@ilande.co.uk> Subject: Re: [Qemu-devel] [PATCH 5/5] cmd646: synchronise UDMA interrupt status with DMA interrupt status List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Cave-Ayland Cc: kwolf@redhat.com, Stefan Hajnoczi , qemu-devel@nongnu.org --rwEMma7ioTxnRzrJ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Aug 11, 2014 at 04:33:01PM +0100, Mark Cave-Ayland wrote: > On 11/08/14 16:12, Stefan Hajnoczi wrote: >=20 > >On Fri, Aug 08, 2014 at 05:23:36PM +0100, Mark Cave-Ayland wrote: > >>@@ -322,6 +342,10 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev) > >> } > >> > >> /* Set write-to-clear interrupt bits */ > >>+ dev->wmask[CFR] =3D 0x0; > >>+ dev->w1cmask[CFR] =3D CFR_INTR_CH0; > >>+ dev->wmask[ARTTIM23] =3D 0x0; > >>+ dev->w1cmask[ARTTIM23] =3D ARTTIM23_INTR_CH1; > >> dev->wmask[MRDMODE] =3D 0x0; > >> dev->w1cmask[MRDMODE] =3D MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1; > > > >It is not clear to me why the mask for MRDMODE has both Channel 0 and 1 > >but the ARTTIM23 and CFR masks only have one channel each. > > > >Please post a link to the datasheet. >=20 > Hi Stefan, >=20 > Thanks for the review. You can find a copy of the 646U2 datasheet at > http://gkernel.sourceforge.net/specs/sii/PCI0646U2Specr030399.PDF.bz2. >=20 > My understanding from the datasheet is that CFR is the primary channel > interrupt whilst ARTTIM23 is the secondary channel interrupt, and the note > on page 28 explains that these bits are also accessible via the relevant > bits of the MRDMODE register. >=20 > This fixes cmd646 under NetBSD since it programs UDMA via MRDMODE but cle= ars > the interrupts via CFR and ARTTIM23, so without this patchset the driver > hangs because the interrupt isn't properly cleared across both registers. > And I can also verify that Linux experiences no regressions with this > patchset applied. Great, thanks! Stefan --rwEMma7ioTxnRzrJ Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBAgAGBQJT6dSUAAoJEJykq7OBq3PIjcIH/1v4IUK+J2rCSkbX71soxBmJ OcfanxX57GLDCTUSjN2zbixqsgqIYzNqdCNNN9kIH3m9FzbcQWBkTQefUOLxvgFV m6B8jB7TNsW5mlydptJ68nhZGf3gUWYfcohn9tRuzf102SEhjA8kRJCWJmFhUxwK m3VCCHk9ktB0Bl3H27i8KzrP37qtXaRZ8BE8UxGQ4h6jpSQOdCQhAVnatDF/hyxH g5oj026PSjM/5mcbftjZeGO5clpdKW46P7ebzZlxdKgy45lMV1r0ChbZ/m82eTM5 LcfG5MNL3duOW5aQfjQM0WVrobUzd7QAGh2PODLUyHDYiPoe1u3pVMKonNGGJnQ= =Q0FC -----END PGP SIGNATURE----- --rwEMma7ioTxnRzrJ--