From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40755) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHpIz-0000TX-3j for qemu-devel@nongnu.org; Thu, 14 Aug 2014 03:18:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XHpIs-0001um-UM for qemu-devel@nongnu.org; Thu, 14 Aug 2014 03:18:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:14791) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHpIs-0001uh-LY for qemu-devel@nongnu.org; Thu, 14 Aug 2014 03:18:30 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s7E7IT5A026030 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Thu, 14 Aug 2014 03:18:30 -0400 Date: Thu, 14 Aug 2014 09:19:05 +0200 From: "Michael S. Tsirkin" Message-ID: <20140814071905.GC30545@redhat.com> References: <1407966975-3723-1-git-send-email-jsnow@redhat.com> <1407966975-3723-3-git-send-email-jsnow@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1407966975-3723-3-git-send-email-jsnow@redhat.com> Subject: Re: [Qemu-devel] [PATCH v3 26/32] ahci: MSI capability should be at 0x80, not 0x50. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: John Snow Cc: qemu-devel@nongnu.org, stefanha@redhat.com, armbru@redhat.com On Wed, Aug 13, 2014 at 05:56:09PM -0400, John Snow wrote: > In the Intel ICH9 data sheet, the MSI capability offset > in the PCI configuration space for ICH9 AHCI devices is > specified to be 0x80. > > Further, the PCI capability pointer should always point > to 0x80 in ICH9 devices, despite the fact that AHCI 1.3 > specifies that it should be pointing to PMCAP (Which in > this instance would be 0x70) to maintain adherence to > the Intel data sheet specifications and real observed behavior. > > Signed-off-by: John Snow Besides the comment I sent previously: Reviewed-by: Michael S. Tsirkin > --- > hw/ide/ich.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/hw/ide/ich.c b/hw/ide/ich.c > index a2f1639..d2a3ac2 100644 > --- a/hw/ide/ich.c > +++ b/hw/ide/ich.c > @@ -71,6 +71,7 @@ > #include > #include > > +#define ICH9_MSI_CAP_OFFSET 0x80 > #define ICH9_SATA_CAP_OFFSET 0xA8 > > #define ICH9_IDP_BAR 4 > @@ -115,7 +116,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev) > /* XXX Software should program this register */ > dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ > > - msi_init(dev, 0x50, 1, true, false); > d->ahci.irq = pci_allocate_irq(dev); > > pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO, > @@ -135,6 +135,9 @@ static int pci_ich9_ahci_init(PCIDevice *dev) > (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4)); > d->ahci.idp_offset = ICH9_IDP_INDEX; > > + /* MSI cap should be added last to be first. */ > + msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false); > + > return 0; > } > > -- > 1.9.3